DFL PCI Express Subsystem IP Driver¶
Last updated: July 01, 2024
Upstream Status: Upstreamed
Devices supported: Stratix 10, Agilex 7
Introduction¶
This driver enables PCIe functionality for PCIe based FPGA solutions that implement the DFL. This driver provides interfaces for user-space applications to configure, enumerate, open and access FPGA accelerators on the FPGA DFL devices, enables system level management functions such as FPGA partial reconfiguration, power management and virtualization with DFL framework.
The dfl-pci driver is a DFL specific instantiation of the generic pci.ko driver.
| Driver | Mapping | Source(s) | Required for DFL |
|---|---|---|---|
| dfl-pci.ko | FPGA DFL PCIe Device Driver | drivers/fpga/dfl-pci.c | Y |
Agilex 7 PCIe Susbystem¶
The PCIe Subsystem is one of three subsystems supported by the OFS FIM. It contains configuration registers for the Vendor, Device and Subsystem Vendor IDs. These registers are used in PCIe add-in cards to uniquely identify the card for assignment to software drivers.
The host-side PCIe SS supports PCIe Gen 4x16 speeds using an AXI-ST Data mover interface across a hardened P-Tile. Is natively supports multiple configurations - including 2 PFs, and 1 PF with multiple VFs. It contains optional support for DMA engines and Single-root I/O Virtualization (SR-IOV). Full documentation on the FPGA IP Subsystem for PCI Express IP User Guide can be found on the Open FPGA Stack Git site.
Driver Sources¶
The GitHub source code for this driver can be found at https://github.com/OFS/linux-dfl/blob/master/drivers/fpga/dfl-pci.c.
The Upstream source code for this driver can be found at https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/fpga/dfl-pci.c?h=master.
Driver Capabilities¶
- Initialize DFL-enabled PCIe SS instances
- Probe for DFLs in PCIe BAR space, and enumerate their features
- Configure SR-IOV
Kernel Configurations¶
FPGA_DFL_PCI
Known Issues¶
None known
Example Designs¶
The PCIe SS is included as a part of the FIM design for PCIe Attach supporting DFL, Stratix 10 PCIe Attach, and SoC Attach. Please refer to site for more information about these designs.
Notices & Disclaimers¶
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Created: May 25, 2024