Ethernet Subsystem (HSSI) Driver for Hard Processor System¶
Last updated: July 11, 2024
Upstream Status: Not Upstreamed
Devices supported: Agilex 7
Introduction¶
The Ethernet Subsystem FPGA IP driver acts as a bridge between the software operating in the HPS and the Ethernet Subsystem within the FPGA. It provides various levels of abstraction to simplify communication with the underlying Ethernet Subsystem IP. The Ethernet Subsystem driver exposes Ethernet netdev driver APIs that higher-level software layers can utilize to interact with the Ethernet Subsystem IP
Ethernet Subsystem FPGA IP¶
The Ethernet Subsystem FPGA IP is a subsystem IP that includes a configurable, Media Access Control (MAC) and Physical Coding Sublayer (PCS) presenting a consistent interface to user logic. It consists of 20 ports. Depending on the tile chosen, each port is implemented based on either the Agilex® 7 E-Tile Hard IP for Ethernet FPGA IP Core or the F-Tile Hard IP for Ethernet FPGA IP core.
This IP provides a seamless and fast way to instantiate a multi-port design, given that it integrates the required discrete Hard IP and Soft IP ingredients. Furthermore, the Subsystem IP provides a user interface to facilitate enabling required features and parameters of operation.
For E-Tile, this subsystem IP provides Ethernet data rate profiles of 10Gbps, 25Gbps, and 100Gbps with optional RS-FEC and 1588 Precision Time Protocol (PTP). The subsystem also provides profiles for PCS, OTN, FlexE and CPRI.
For F-Tile, this subsystem IP provides Ethernet data rate profiles of 10Gbps, 25Gbps, 40Gbps, 50Gbps, 100Gbps, 200Gbps, and 400Gbps with optional RS-FEC and 1588 Precision Time Protocol (PTP). Quartus® Prime software version 23.2 supports only Media Access Control (MAC) and Physical Coding Sublayer (PCS) sub-profile.
For more information please refer to the Ethernet Subsystem FPGA IP User Guide.
Driver Sources¶
The source code for this driver can be found at:
Driver Capabilities¶
- Get Link state.
- Get MAC stats. These abstractions are used by the HSSI ethernet netdev driver to provide ethernet functionality to the above layers.
Kernel Configurations¶
CONFIG_INTEL_FPGA_HSSISS
Device Tree¶
Example Device tree location to configure the HSSI:
Known Issues¶
None known
Example Designs¶
HSSI SS driver is used in the Agilex 7 SoC F-Tile Design Example for 25/10 GbE with IEEE1588PTP.
Notices & Disclaimers¶
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Created: May 25, 2024