A Modular Scatter-Gather DMA (mSGDMA) Driver for Hard Processor System¶
Last updated: July 01, 2024
Upstream Status: Not Upstreamed
Devices supported: Agilex 7
Introduction¶
In a processor subsystem, data transfers between two memory spaces can happen frequently. In order to offload the processor from moving data around a system, a Direct Memory Access (DMA) engine is introduced to perform this function instead. The Modular Scatter-Gather DMA (mSGDMA) is capable of performing data movement operations with preloaded instructions, called descriptors. Multiple descriptors with different transfer sizes, and source and destination addresses have the option to trigger interrupts.
mSGDMA FPGA IP¶
The mSGDMA provides three configuration structures for handling data transfers: between the Avalon-MM to Avalon-MM, Avalon-MM to Avalon-ST, and Avalon-ST to Avalon-MM. The sub-core of the mSGDMA is instantiated automatically according to the structure configured for the mSGDMA use model. For more information on MSGDMA IP core please refer to https://www.intel.com/content/www/us/en/docs/programmable/683130/23-1/modular-scatter-gather-dma-core.html.
Driver Sources¶
The source code for this driver can be found at:
Driver Capabilities¶
- Manage multiple DMA channels provided by the MSGDMA IP core.
- Provides support for interrupt handling.
- Provides support for Scatter-gather DMA operation through a set of buffer descriptors.
- Data transfer to non-contiguous memory space.
Kernel Configurations¶
CONFIG_ALTERA_MSGDMA
Known Issues¶
None Known
Example Designs¶
Moified version of MSGDMA driver is used in the Agilex 7 SoC F-Tile Design Example for 25/10 GbE with IEEE1588PTP and also the source code is available at https://github.com/altera-opensource/linux-socfpga/tree/socfpga-6.1.55-lts/drivers/net/ethernet/altera.
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Created: May 25, 2024