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Agilex™ 5 E-Series Modular Development Kit GSRD User Guide

Introduction

GSRD Overview

The Golden System Reference Design (GSRD) is a reference design running on the Agilex 5 E-Series Modular Development Kit.

The GSRD is comprised of the following components:

  • Golden Hardware Reference Design (GHRD)
  • Reference HPS software including:
    • Arm Trusted Firmware
    • U-Boot
    • Linux Kernel
    • Linux Drivers
    • Sample Applications

Prerequisites

The following are required to be able to fully exercise the Agilex 5 Modular Development Kit GSRD:

  • Altera Agilex 5 FPGA E-Series 065B Modular Development Kit, ordering code MK-A5E065BB32AES1. Refer to board documentation for more information about the development kit.
    • Power supply
    • 2 x Micro USB Cable
    • Ethernet Cable
    • Micro SD card and USB card writer
  • Host PC with
    • 64 GB of RAM. Less will be fine for only exercising the binaries, and not rebuilding the GSRD.
    • Linux OS installed. Ubuntu 22.04LTS was used to create this page, other versions and distributions may work too
    • Serial terminal (for example GtkTerm or Minicom on Linux and TeraTerm or PuTTY on Windows)
    • Intel Quartus Prime Pro Edition version. Used to recompile the hardware design. If only writing binaris is required, then the smaller Intel Quartus Prime Pro Edition Programmer is sufficient.
      • The prebuilt binaries were built using Quartus version 24.2
      • The instructions for rebuilding the binaries use Quartus version 24.2
  • Local Ethernet network, with DHCP server
  • Internet connection. For downloading the files, especially when rebuilding the GSRD.

Release Contents

This page documents the following:

Release Notes

See https://www.rocketboards.org/foswiki/Documentation/IntelFPGAHPSEmbeddedSoftwareRelease

Development Kit

This release targets the Agilex 5 FPGA E-Series 065B Modular Development Kit. It is composed of a carrier board which offers additional connectivity, and a SOM board which contains the FPGA part, HPS DDRAM and all other required circuitry. Refer to board documentation for more information about the development kit.

Changing MSEL

MSEL signals instruct the FPGA device on which configuration scheme to use. Configuration schemes used by the scenarios presented in this guide are JTAG and ASx4 (QSPI). MSEL is changed through dipswitch S4 on the top left cornet of the SOM board. Only change the settings while the board is powered off.

The MSEL settings are:

  • JTAG: SW4[2:1]=OFF:OFF
  • ASx4 (QSPI): SW4[2:1]=ON:ON

GHRD Overview

The Golden Hardware Reference Design is an important part of the GSRD and consists of the following components:

  • Hard Processor System (HPS)
    • Dual core Arm Cortex-A76 processor
    • Dual core Arm Cortex-A55 processor
    • HPS Peripherals
      • Micro SD Card
      • EMAC
      • HPS JTAG debug
      • UART
      • I2C
      • USB 3.1
  • Multi-Ported Front End (MPFE) for HPS External Memory Interface (EMIF)
  • FPGA Peripherals connected to Lightweight HPS-to-FPGA (LWH2F) AXI Bridge and JTAG to Avalon Master Bridge
    • One user LED output
    • Two user DIP switch inputs
    • One user push-button input
    • System ID
  • FPGA Peripherals connected to HPS-to-FPGA (H2F) AXI Bridge
    • 256KB of FPGA on-chip memory

The GHRD allows hardware designers to access each peripheral in the FPGA portion of the SoC with System Console, through the JTAG master module. This signal-level access is independent of the driver readiness of each peripheral.

MPU Address Maps

This section presents the address maps as seen from the MPU side.

HPS-to-FPGA Address Map

The three FPGA windows in the MPU address map provide access to 256 GB of FPGA space. First window is 1 GB from 00_4000_0000, second window is 15 GB from 04_4000_0000, third window is 240 GB from 44_0000_0000. The following table lists the offset of each peripheral from the HPS-to-FPGA bridge in the FPGA portion of the SoC.

Peripheral Address Offset Size (bytes) Attribute
onchip_memory2_0 0x0 256K On-chip RAM as scratch pad
Lightweight HPS-to-FPGA Address Map

The the memory map of system peripherals in the FPGA portion of the SoC as viewed by the MPU, which starts at the lightweight HPS-to-FPGA base address of 0x00_2000_0000, is listed in the following table.

Peripheral Address Offset Size (bytes) Attribute
sysid 0x0001_0000 32 Unique system ID
button_pio 0x0001_0060 16 Push button inputs
dipsw_pio 0x0001_0070 16 DIP switch inputs
led_pio 0x0001_0080 16 LED outputs
JTAG Master Address Map

There are three JTAG master interfaces in the design, one for accessing non-secure peripherals in the FPGA fabric, and another for accessing secure peripheral in the HPS through the FPGA-to-HPS Interface and another for FPGA fabric to SDRAM.

The following table lists the address of each peripheral in the FPGA portion of the SoC, as seen through the non-secure JTAG master interface.

Peripheral Address Offset Size (bytes) Attribute
onchip_memory2_0 0x0004_0000 256K On-chip RAM
sysid 0x0001_0000 32 Unique system ID
button_pio 0x0001_0060 16 Push button inputs
dipsw_pio 0x0001_0070 16 DIP switch inputs
led_pio 0x0001_0080 16 LED outputs

Interrupt Routing

The HPS exposes 64 interrupt inputs for the FPGA logic. The following table lists the interrupt connections from soft IP peripherals to the HPS interrupt input interface.

Peripheral Interrupt Number Attribute
dipsw_pio f2h_irq0[1] DIP switch input
button_pio f2h_irq0[0] Push button input

Exercising Prebuilt Binaries

This section presents how to use the prebuilt binaries included with the GSRD release.

Prebuilt Release Contents

Binaries

The Agilex 5 Modular Development Kit 24.2 GSRD binaries are located at https://releases.rocketboards.org/2024.07/:

Boot Source Link
SD Card https://releases.rocketboards.org/2024.07/gsrd/agilex5_modular_gsrd/
QSPI https://releases.rocketboards.org/2024.07/qspi/agilex5_modular_qspi/

Sources

Quartus Prime Pro v24.2 and the following software component versions were used to build the provided prebuilt binaries:

Component Location Branch Commit ID/Tag
GHRD https://github.com/altera-opensource/ghrd-socfpga master QPDS24.2_REL_AGILEX5_GSRD_PR
Linux https://github.com/altera-opensource/linux-socfpga socfpga-6.6.22-lts QPDS24.2_REL_AGILEX5_GSRD_PR
Arm Trusted Firmware https://github.com/altera-opensource/arm-trusted-firmware socfpga_v2.10.1 QPDS24.2_REL_AGILEX5_GSRD_PR
U-Boot https://github.com/altera-opensource/u-boot-socfpga socfpga_v2024.01 QPDS24.2_REL_AGILEX5_GSRD_PR
Yocto Project: poky https://git.yoctoproject.org/poky scarthgap latest
Yocto Project: meta-intel-fpga https://git.yoctoproject.org/meta-intel-fpga scarthgap QPDS24.2_REL_AGILEX5_GSRD_PR
Yocto Project: meta-intel-fpga-refdes https://github.com/altera-opensource/meta-intel-fpga-refdes scarthgap QPDS24.2_REL_AGILEX5_GSRD_PR
GSRD Build Script: gsrd-socfpga https://github.com/altera-opensource/gsrd-socfpga scarthgap QPDS24.2_REL_AGILEX5_GSRD_PR

Configure Board

1. Leave all jumpers and switches in their default configuration.

2. Connect micro USB cable from bottom left of the carrier board to PC. This will be used for JTAG communication.

3. Connect micro USB cable from bottom right of the SOM board to PC. This will be used for HPS UART communication.

4. Connect Ethernet cable from SOM board to an Ethernet switch connected to local network. Local network must provide a DCHP server.

Configure Serial Console

All the scenarios included in this release require a serial connection. This section presents how to configure the serial connection.

Each of the USB connections listed above will enumerate 4 USB serial ports on your host computer. The HPS UART port is the 3rd one enumerated by the connection to the SOM board.

1. Install a serial terminal emulator application on your host PC:

  • For Windows: TeraTerm or PuTTY are available
  • For Linux: GtkTerm or Minicom are available

2. Remove USB cables, and power down your board if powered up. Look at what USB serial ports are enumerated on your computer by default, without board being connected.

3. Power up the board.

4. Connect micro USB cable from bottom left of the carrier board to PC. This will be used for JTAG communication. Look at what ports are enumerated on your host computer, there should be a series of four.

5. Connect micro USB cable from bottom right of the SOM board to PC. This will be used for HPS UART communication. Look at what ports are enumerated on your host computer, there should be a series of four. Use the 3rd one in the list as the HPS serial port.

Possible serial port allocation in Windows

  • COM3: already there before board was installed
  • COM4-7: enumerated by the JTAG connection
  • COM8-11: enumerated by the HPS connection

In the above case, the port to use for HPS serial communication would be COM10.

Possible serial port allocation in Linux

  • /dev/ttyUSB0-3: enumerated by the JTAG connection
  • /dev/ttyUSB4-7:enumerated by the HPS connection

In the above case, the port to use for HPS serial communication would be /dev/ttyUSB6.

Notes:

  • On Windows, the port number may be kept between power cycles, but not always.
  • On Linux, the port numbe may change depending on the order in which cables are inserted.

6. Configure your serial terminal emulator to use the following settings:

  • Serial port: as mentioned above
  • Baud rate: 115,200
  • Data bits: 8
  • Stop bits: 1
  • CRC: disabled
  • Hardware flow control: disabled

7. Connect your terminal emulator

Booting from SD Card

Write SD Card

1. Download SD card image from the prebuilt binaries https://releases.rocketboards.org/2024.07/gsrd/agilex5_modular_gsrd/sdimage.tar.gz and extract the archive, obtaining the file gsrd-console-image-agilex5_devkit.wic.

2. Write the gsrd-console-image-agilex5_devkit.wic. SD card image to the micro SD card using the included USB writer in the host computer:

  • On Linux, use the dd utility as shown next: 
    # Determine the device asociated with the SD card on the host computer. 
cat /proc/partitions
# This will return for example /dev/sdx
# Use dd to write the image in the corresponding device
sudo dd if=gsrd-console-image-agilex5_devkit.wic of=/dev/sdx bs=1M
# Flush the changes to the SD card
sync
  • On Windows, use the Win32DiskImager program, available at https://win32diskimager.org/. For this, first rename the gsrd-console-image-agilex5_devkit.wic to an .img file (sdcard.img for example) and write the image as shown in the next figure:

Write QSPI Flash

1. Power down board

2. Set MSEL dipswitch S4 on SOM to JTAG: OFF-OFF

3. Power up the board

4. Download and extract the JIC image, then write it to QSPI 

wget https://releases.rocketboards.org/2024.07/gsrd/agilex5_modular_gsrd/ghrd_a5ed065bb32ae6sr0.hps.jic.tar.gz
tar xf ghrd_a5ed065bb32ae6sr0.hps.jic.tar.gz
quartus_pgm -c 1 -m jtag -o "pvi;ghrd_a5ed065bb32ae6sr0.hps.jic"

Boot Linux

1. Power down board

2. Set MSEL dipswitch S4 on SOM to ASX4 (QSpI): ON-ON

3. Power up the board

4. Wait for Linux to boot, use root as user name, and no password wil be requested.

Run Sample Applications

1. Boot to Linux

2. Change current folder to intelFPGA folder 

cd intelFPGA
3. Run the hello world application 
./hello
4. Run the syscheck application 
./syscheck
Press q to exit the syscheck application.

Control LED

1. Boot to Linux

2. Control LED by using the following sysfs entries:

  • /sys/class/leds/fpga_led0/brightness
  • /sys/class/leds/hps_led1/brightness

using commands such as: 

cat /sys/class/leds/fpga_led0/brightness
echo 0 > /sys/class/leds/fpga_led0/brightness
echo 1 > /sys/class/leds/fpga_led1/brightness

Because of how the LEDs are connected, for the above commands 0 means LED is turned on, 1 means LED is turned off.

Connect to Board Using SSH

1. Boot to Linux

2. Determine the board IP address using the ifconfig command: 

root@agilex5devkit:~# ifconfig
eth0: flags=-28605<UP,BROADCAST,RUNNING,MULTICAST,DYNAMIC>  mtu 1500
        inet 192.168.1.153  netmask 255.255.255.0  broadcast 192.168.1.255
        inet6 fe80::f0eb:c8ff:fec4:eed7  prefixlen 64  scopeid 0x20<link>
        ether f2:eb:c8:c4:ee:d7  txqueuelen 1000  (Ethernet)
        RX packets 649  bytes 45132 (44.0 KiB)
        RX errors 0  dropped 226  overruns 0  frame 0
        TX packets 56  bytes 8789 (8.5 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
        device interrupt 23  

lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536
        inet 127.0.0.1  netmask 255.0.0.0
        inet6 ::1  prefixlen 128  scopeid 0x10<host>
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 100  bytes 8408 (8.2 KiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 100  bytes 8408 (8.2 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
3. Connect to the board over SSH using root username, no password will be requested: 
ssh root@192.168.1.153
Note: Make sure to replace the above IP address to the one matching the output of running ifconfig on youir board.

Visit Board Web Page

1. Boot to Linux

2. Determine board IP address using ifconfig like in the previous scenario

3. Start a web browser and enter the IP address in the address bar

4. The web browser will display a page served by the web server running on the board.

Note: Current release has a limitation, in that the LEDs are not controllable from the web page. This will be resolved in the next release.

Booting from QSPI

This section presents how to boot from QSPI. One notable aspect is that you need to wipe the SD card partitioning information, as otherwise U-Boot SPL could find a valid SD card image, and try to boot from that first.

Wipe SD Card

Either write 1MB of zeroes at the beginning of the SD card, or remove the SD card from the HPS Daughter Card. You can use dd on Linux, or Win32DiskImager on Windows to achieve this.

Write QSPI Flash

1. Power down board

2. Set MSEL dipswitch S4 on SOM to JTAG: OFF-OFF

3. Power up the board

4. Download and extract the JIC image, then write it to QSPI: 

wget https://releases.rocketboards.org/2024.07/qspi/agilex5_modular_qspi/agilex_flash_image.hps.jic.tar.gz
tar xf agilex_flash_image.hps.jic.tar.gz
quartus_pgm -c 1 -m jtag -o "pvi;agilex_flash_image.hps.jic"

Boot Linux

1. Power down board

2. Set MSEL dipswitch S4 on SOM to ASX4 (QSpI): ON-ON

3. Power up the board

4. Wait for Linux to boot, use root as user name, and no password wil be requested.

Note: On first boot, the UBIFS rootfilesystem is initialized, and that takes a few minutes. This will not happen on next reboots. See a sample log below:

[   17.033558] UBIFS (ubi0:4): Mounting in unauthenticated mode
[   17.039470] UBIFS (ubi0:4): background thread "ubifs_bgt0_4" started, PID 130
[   17.061510] UBIFS (ubi0:4): start fixing up free space
[   20.644496] random: crng init done
[   27.120040] platform soc:leds: deferred probe pending
[  243.190874] UBIFS (ubi0:4): free space fixup complete
[  243.315909] UBIFS (ubi0:4): UBIFS: mounted UBI device 0, volume 4, name "rootfs"
[  243.323290] UBIFS (ubi0:4): LEB size: 65408 bytes (63 KiB), min./max. I/O unit sizes: 8 bytes/256 bytes
[  243.332653] UBIFS (ubi0:4): FS size: 167117440 bytes (159 MiB, 2555 LEBs), max 6500 LEBs, journal size

Rebuilding the GSRD

Component Versions

Quartus Prime Pro v24.2 and the following software component versions were used to build the provided prebuilt binaries:

Component Location Branch Commit ID/Tag
GHRD https://github.com/altera-opensource/ghrd-socfpga master QPDS24.2_REL_GSRD_PR
Linux https://github.com/altera-opensource/linux-socfpga socfpga-6.6.22-lts QPDS24.2_REL_GSRD_PR
Arm Trusted Firmware https://github.com/altera-opensource/arm-trusted-firmware socfpga_v2.10.1 QPDS24.2_REL_GSRD_PR
U-Boot https://github.com/altera-opensource/u-boot-socfpga socfpga_v2024.01 QPDS24.2_REL_GSRD_PR
Yocto Project: poky https://git.yoctoproject.org/poky scarthgap latest
Yocto Project: meta-intel-fpga https://git.yoctoproject.org/meta-intel-fpga scarthgap QPDS24.2_REL_GSRD_PR
Yocto Project: meta-intel-fpga-refdes https://github.com/altera-opensource/meta-intel-fpga-refdes scarthgap QPDS24.2_REL_GSRD_PR
GSRD Build Script: gsrd-socfpga https://github.com/altera-opensource/gsrd-socfpga scarthgap QPDS24.2_REL_GSRD_PR

Yocto Build Prerequisites

Make sure you have Yocto system requirements met: Yocto Requirements.

The command to install the required packages on Ubuntu 22.04-LTS is: 

sudo apt-get update
sudo apt-get upgrade
sudo apt-get install openssh-server mc libgmp3-dev libmpc-dev gawk wget git diffstat unzip texinfo gcc \
build-essential chrpath socat cpio python3 python3-pip python3-pexpect xz-utils debianutils iputils-ping \
python3-git python3-jinja2 libegl1-mesa libsdl1.2-dev pylint3 xterm python3-subunit mesa-common-dev zstd \
liblz4-tool git fakeroot build-essential ncurses-dev xz-utils libssl-dev bc flex libelf-dev bison xinetd \
tftpd tftp nfs-kernel-server libncurses5 libc6-i386 libstdc++6:i386 libgcc++1:i386 lib32z1 \
device-tree-compiler curl mtd-utils u-boot-tools net-tools swig -y
On Ubuntu 22.04 you will also need to point the /bin/sh to /bin/bash, as the default is a link to /bin/dash: 
sudo ln -sf /bin/bash /bin/sh

Build SD Card Boot Binaries

The following diagram shows an overview of how the build process works for this use case:

Setup Environment

1. Create the top folder to store all the build artifacts:

sudo rm -rf gsrd.modular
mkdir gsrd.modular
cd gsrd.modular
export TOP_FOLDER=`pwd`

2. Download and setup the build toolchain. It will be used only by the GHRD makefile to build the debug HPS FSBL, to build the _hps_debug.sof file:

cd $TOP_FOLDER
wget https://developer.arm.com/-/media/Files/downloads/gnu/11.2-2022.02/binrel\
/gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
tar xf gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
rm -f gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
export PATH=`pwd`/gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu/bin:$PATH
export ARCH=arm64
export CROSS_COMPILE=aarch64-none-linux-gnu-

3. Set up the Quartus tools in the PATH, so they are accessible without full path

export QUARTUS_ROOTDIR=~/intelFPGA_pro/24.2/quartus/
export PATH=$QUARTUS_ROOTDIR/bin:$QUARTUS_ROOTDIR/linux64:$QUARTUS_ROOTDIR/../qsys/bin:$PATH
Build Hardware Design
cd $TOP_FOLDER
rm -rf ghrd-socfpga agilex5_soc_devkit_ghrd
git clone -b QPDS24.2_REL_GSRD_PR https://github.com/altera-opensource/ghrd-socfpga
mv ghrd-socfpga/agilex5_soc_devkit_ghrd .
rm -rf ghrd-socfpga
cd agilex5_soc_devkit_ghrd
make config
make BOARD_TYPE=DK-MODULAR DEVICE=A5ED065BB32AE6SR0 DAUGHTER_CARD=mod_som HPS_EMIF_EN=1 HPS_EMIF_MEM_CLK_FREQ_MHZ=800 HPS_EMIF_REF_CLK_FREQ_MHZ=150 INITIALIZATION_FIRST=hps generate_from_tcl
make all
cd ..

The following files are created:

  • $TOP_FOLDER/agilex5_soc_devkit_ghrd/output_files/ghrd_a5ed065bb32ae6sr0.sof
  • $TOP_FOLDER/agilex5_soc_devkit_ghrd/output_files/ghrd_a5ed065bb32ae6sr0_hps_debug.sof
Build Core RBF
cd $TOP_FOLDER
rm -f ghrd_a5ed065bb32ae6sr0.rbf
quartus_pfg -c agilex5_soc_devkit_ghrd/output_files/ghrd_a5ed065bb32ae6sr0_hps_debug.sof ghrd_a5ed065bb32ae6sr0.rbf -o hps=1

The following file is created:

  • $TOP_FOLDER/ghrd_a5ed065bb32ae6sr0.core.rbf
Set Up Yocto

1. Clone the Yocto script and prepare the build:

cd $TOP_FOLDER
rm -rf gsrd-socfpga
git clone -b QPDS24.2_REL_GSRD_PR https://github.com/altera-opensource/gsrd-socfpga
cd gsrd-socfpga
. agilex5_modular-gsrd-build.sh
build_setup
Customize Yocto

1. Save the core.rbf as $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/files/agilex5_modular_gsrd_ghrd.core.rbf

2. Update the recipe $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/hw-ref-design.bb as follows:

  • Replace the entry ${GHRD_REPO}/agilex5_modular_gsrd_${ARM64_GHRD_CORE_RBF};name=agilex5_modular_gsrd_core with file://agilex5_modular_gsrd_ghrd.core.rbf;sha256sum=<CORE_SHA> where CORE_SHA is the sha256 checksum of the file
  • Delete the line SRC_URI[agilex5_modular_gsrd_core.sha256sum] = "bf11c8cb3b6d9487f93ce0e055b1e5256998a25b25ac4690bef3fcd6225ee1ae" The above are achieved by the following instructions:
CORE_RBF=$WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/files/agilex5_modular_gsrd_ghrd.core.rbf
ln -s $TOP_FOLDER/ghrd_a5ed065bb32ae6sr0.core.rbf $CORE_RBF
OLD_URI="\${GHRD_REPO}\/agilex5_modular_gsrd_\${ARM64_GHRD_CORE_RBF};name=agilex5_modular_gsrd_core"
CORE_SHA=$(sha256sum $CORE_RBF | cut -f1 -d" ")
NEW_URI="file:\/\/agilex5_modular_gsrd_ghrd.core.rbf;sha256sum=$CORE_SHA"
sed -i "s/$OLD_URI/$NEW_URI/g" $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/hw-ref-design.bb
sed -i "/agilex5_modular_gsrd_core\.sha256sum/d" $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/hw-ref-design.bb
Build Yocto

Remove reference to patch which was retired after 24.2 tag was applied:

sed -i '/fix-potential-signed-overflow-in-pointer-arithmatic.patch/d' meta-intel-fpga-refdes/recipes-connectivity/openssh/openssh_%.bbappend

Build Yocto:

bitbake_image

Gather files:

package

The following files are created:

  • $TOP_FOLDER/gsrd-socfpga/agilex5_modular-gsrd-images/u-boot-agilex5-socdk-gsrd-atf/u-boot-spl-dtb.hex
  • $TOP_FOLDER/gsrd-socfpga/agilex5_modular-gsrd-images/u-boot.itb
  • $TOP_FOLDER/gsrd-socfpga/agilex5_modular-gsrd-images/sdimage.tar.gz
Build QSPI Image
cd $TOP_FOLDER
rm -f ghrd_a5ed065bb32ae6sr0.hps.jic ghrd_a5ed065bb32ae6sr0.core.rbf
quartus_pfg \
-c agilex5_soc_devkit_ghrd/output_files/ghrd_a5ed065bb32ae6sr0.sof ghrd_a5ed065bb32ae6sr0.jic \
-o device=MT25QU128 \
-o flash_loader=A5ED065BB32AE6SR0 \
-o hps_path=gsrd-socfpga/agilex5_modular-gsrd-images/u-boot-agilex5-socdk-gsrd-atf/u-boot-spl-dtb.hex \
-o mode=ASX4 \
-o hps=1

The following file is created:

  • $TOP_FOLDER/ghrd_a5ed065bb32ae6sr0.hps.jic
Build HPS RBF

This is an optional step, in which you can build an HPS RBF file, which can be used to configure the HPS through JTAG instead of QSPI though the JIC file.

cd $TOP_FOLDER
rm -f ghrd_a5ed065bb32ae6sr0.hps.rbf
quartus_pfg \
-c agilex5_soc_devkit_ghrd/output_files/ghrd_a5ed065bb32ae6sr0.sof  ghrd_a5ed065bb32ae6sr0.rbf \
-o hps_path=gsrd-socfpga/agilex5_modular-gsrd-images/u-boot-agilex5-socdk-gsrd-atf/u-boot-spl-dtb.hex \
-o hps=1

The following file is created:

  • $TOP_FOLDER/ghrd_a5ed065bb32ae6sr0.hps.rbf

Build QSPI Boot Binaries

The diagram below shows how booting from QSPI JIC is built. The hardware project compilation and Yocto build remain the same, and the QSPI JIC is built based on the resulted files:

1. Create the folder to contain all the files:

cd $TOP_FOLDER
sudo rm -rf qspi_boot
mkdir qspi_boot
cd qspi_boot

2. Get the ubinize.cfg file which contains the details on how to build the root.ubi volume, and agilex5_devkit_flash_image_hps.pfg which contains the instructions for Programming File Generator on how to create the .jic file:

wget https://releases.rocketboards.org/2024.05/qspi/agilex5_dk_a5e065bb32aes1_qspi/ubinize.cfg
wget https://releases.rocketboards.org/2024.05/qspi/agilex5_dk_a5e065bb32aes1_qspi/agilex5_devkit_flash_image_hps.pfg

3. Link to the files that are needed from building the hardware design, and yocto:

ln -s $TOP_FOLDER/gsrd-socfpga/agilex5_modular-gsrd-images/console-image-minimal-agilex5_nor.ubifs rootfs.ubifs
ln -s $TOP_FOLDER/gsrd-socfpga/agilex5_modular-gsrd-images/kernel.itb .
ln -s $TOP_FOLDER/gsrd-socfpga/agilex5_modular-gsrd-images/u-boot-agilex5-socdk-gsrd-atf/boot.scr.uimg
ln -s $TOP_FOLDER/gsrd-socfpga/agilex5_modular-gsrd-images/u-boot-agilex5-socdk-gsrd-atf/u-boot-spl-dtb.hex .
ln -s $TOP_FOLDER/agilex5_soc_devkit_ghrd/output_files/ghrd_a5ed065bb32ae6sr0.sof .

4. Process the u-boot.itb file to be exactly 2MB in size:

cp $TOP_FOLDER/gsrd-socfpga/agilex5_modular-gsrd-images/u-boot-agilex5-socdk-gsrd-atf/u-boot.itb .
uboot_part_size=2*1024*1024
uboot_size=`wc -c < u-boot.itb`
uboot_pad="$((uboot_part_size-uboot_size))"
truncate -s +$uboot_pad u-boot.itb
mv u-boot.itb u-boot.bin

5. Create the root.ubi file and rename it to hps.bin as Programming File Generator needs the .bin extension:

ubinize -o root.ubi -p 65536 -m 1 -s 1 ubinize.cfg
ln -s root.ubi hps.bin

6. Create the JIC file:

quartus_pfg -c agilex5_devkit_flash_image_hps.pfg

The following file is created:

  • $TOP_FOLDER/qspi_boot/agilex_flash_image.hps.jic
Last update: September 23, 2024
Created: August 7, 2024