Direct Memory Access Controller (DMAC) Driver for Hard Processor System¶
Last updated: February 12, 2025
Upstream Status: Upstreamed
Devices supported: Agilex 5
Introduction¶
The DMAC driver supports two DMACs with a maximum of four channels each. This driver transfers data between memory and peripherals and other memory locations in the system.
HPS Direct Memory Access Controller (DMAC)¶
The DMAC is part of the Hard Processor System (HPS) of the FPGA. The HPS provides two DMACs to handle the data transfer between memory-mapped peripherals and memories, off-loading this work from the MPU system complex. Some common features are listed below.
- Software programmable with dedicated register field
- Supports multiple transfer types
- Each DMAC channels supports four channels
- Each DMAC supports interrupt interface to the Generic Interrupt Controller (GIC)
- Supports up to 48 peripheral request interfaces
For more information please refer to the following guide: Agilex 5 Hard Processor System Technical Reference Manual
Driver Sources¶
The source code for this driver can be found at
Driver Capabilities¶
- DMA bus width configuration
- Transaction configuration
- Interrupt control and handling
Kernel Configurations¶
CONFIG_DW_AXI_DMAC
Device Tree¶
Example Device tree location to configure the dma: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
Known Issues¶
None known
Notices & Disclaimers¶
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Created: May 25, 2024