Error Detection and Correction (EDAC) Driver for Hard Processor System¶
Last updated: February 12, 2025
Upstream Status: Upstreamed
Devices supported: Agilex 5
Introduction¶
The Error Detection and Correction (EDAC) driver supports use of the Error Checking and Correction (ECC) Controller in the HPS. The ECC controllers are implemented in the on-chip RAM, USB OTG 2.0 and 3.1 and Ethernet MACs in the HPS. To find out more about the ECC controller please refer to the Hard Processor Technical Reference Manual.
Driver Sources¶
The source code for the driver can be found at https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/edac/altera_edac.c.
Driver Capabilities¶
The Error Detection and Correction (EDAC) driver comprises the ECC manager main component and sub-components of the supported EDAC SoC components.
The driver's main functions are to register the EDAC platform drivers in Linux, initialize the EDAC sub-components by performing initial setup of the IRQ interrupt handlers and soft-error handling for uncorrected error events, and to support debugging features like soft-error injections and reads of the error counters.
The data flow diagram of EDAC is shown below:
Kernel Configurations¶
CONFIG_EDAC_ALTERA
Known Issues¶
None known
Notices & Disclaimers¶
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Created: May 25, 2024