Ethernet Subsystem Intel FPGA IP Tile Specific Ethernet MAC Driver for Hard Processor System¶
Last updated: February 12, 2025
Upstream Status: Not Upstreamed
Devices supported: Agilex 7
Introduction¶
The Ethernet MAC driver is used to manage the configuration parameters of the particular tile. It currently supports F-tile and E-tile of the Ethernet Subsystem Intel FPGA IP
F-tile and E-tile FPGA IP¶
To get more information on F-tile Hard IP please refer to the F-tile Architecture and PMA and FEC Direct PHY IP User Guide.
And for E-tile Hard IP please refer to the E-Tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY IPs.
Driver Sources¶
The source code to generate intel_fpga_hssi_xtile.o can be found at the following directory location:
graph TD;
A[intel_fpga_hssi_xtile.o]-->B[intel_fpga_eth_main.c];
A[intel_fpga_hssi_xtile.o]-->C[intel_fpga_hssi_etile_fec.c];
A[intel_fpga_hssi_xtile.o]-->D[intel_fpga_etile_driver.c];
A[intel_fpga_hssi_xtile.o]-->E[intel_fpga_hssi_etile_ethtool.c];
A[intel_fpga_hssi_xtile.o]-->F[intel_fpga_ftile_driver];
A[intel_fpga_hssi_xtile.o]-->G[intel_fpga_hssi_ftile_fec.c];
A[intel_fpga_hssi_xtile.o]-->H[intel_fpga_hssi_ftile_ethtool.c];Driver Capabilities¶
- To set the tile specific parameters, like enable support for interrupts, DMA and also the ethtool related configuration.
Kernel Configurations¶
CONFIG_INTEL_FPGA_HSSI_XTILE
Device Tree¶
Example of Device tree location to configure the hssi_xtile:
Known Issues¶
None known
Example Designs¶
HSSI xtile (E-tile/F-tile) driver is used in the Agilex 7 SoC F-Tile Design Example for 25/10 GbE with IEEE1588PTP
Notices & Disclaimers¶
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Created: May 25, 2024