NAND Flash Controller Driver for Hard Processor System¶
Last updated: February 12, 2025
Upstream Status: Upstreamed
Devices supported: Agilex 5
Introduction¶
The Hard Processor System (HPS) provides a NAND Flash controller to interface with external NAND Flash memory in Intel system-on-a-chip (SoC) systems. External Flash memory can be used to store software, or as extra storage capacity for large applications or user data. For more information please refer to the Intel Agilex 5 Hard Processor System Technical Reference Manual.
Features¶
- The triple-level cell (TLC) devices are supported only in parts that are compatible with the ONFI specification
- Supports three operation modes that make the controller easy to operate while also providing enough flexibility to be adapted to your project's needs.
- Supports DMA data transfer which optimizes the transfer rate for read and write operations using DMA primary and DMA secondary interfaces.
- Supports devices with page sizes up to 64 KB.
- Support up to 8 operation threads that can be executed in parallel.
- Provides data buffering where necessary in order to achieve maximum performance.
Driver Sources¶
The source code for this driver can be found at https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/mtd/nand/raw/cadence-nand-controller.c.
Driver Capabilities¶
- Initialization and configuration of the NAND controller hardware.
- Determine the characteristics like page size and block size.
Kernel Configurations¶
CONFIG_MTD_NAND_CADENCE
Device Tree¶
Example Device tree location:
https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
Known Issues¶
None known
Notices & Disclaimers¶
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Created: May 25, 2024