Watchdog Timers Driver for Hard Processor System¶
Last updated: September 03, 2024
Upstream Status: Upstreamed
Device Supported: Agilex 5
Introduction¶
The watchdog timers are peripherals you can use to recover from system lockup that might be caused by software or system related issues. The hard processor system (HPS) provides five programmable watchdog timers, which are connected to the level 4 (L4) peripheral bus.
Each watchdog timer consists of a slave interface for control and status register (CSR) access, a register block, and a 32-bit down counter that operates on the slave interface clock (l4_sys_free_clk). A pause input, driven by the system manager, optionally pauses the counter when a CPU is being debugged.The watchdog timer drives an interrupt request to the MPU and a reset request to the reset manager.
For more information please refer to the Agilex 5 Hard Processor System Technical Reference Manual.
Driver Sources¶
The source code for this driver can be found at https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/watchdog/dw_wdt.c.
Driver Capabilities¶
- Allows configuration of the watchdog timer timeout period, specifying the duration after which the watchdog will trigger a system reset if not reset by the software
- Initializes the watchdog timer hardware during system boot, setting up the necessary registers and configurations to enable watchdog functionality.
- Handles interrupts generated by the watchdog timer hardware, allowing the system to respond appropriately to watchdog events, such as timer expiration.
Kernel Configurations¶
CONFIG_DW_WATCHDOG
Device Tree¶
Example Device tree location:
Known Issues¶
None known
Notices & Disclaimers¶
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Created: May 25, 2024