I2C Driver for Hard Processor System¶
Last updated: April 24, 2025
Upstream Status: Upstreamed
Devices supported: Agilex 7, Agilex 5
Introduction¶
The I2C controller provides support for a communication link between integrated circuits on a board. It is a simple two-wire bus which consists of a serial data line (SDA) and a serial clock (SCL).
The hard processor system (HPS) provides five I2C controllers to enable system software to communicate serially with I2C buses. Each I2C controller can operate in master or slave mode and support standard mode of up to 100 Kbps or fast mode of up to 400 Kbps. These I2C controllers are instances of the Synopsys DesignWare controller.
Each I2C controller must be programmed to operate in either master or slave mode only. Operating as a master and slave simultaneously is not supported.
For More information please refer to the following link:
Agilex 5 Hard Processor System Technical Reference Manual
Driver Sources¶
The source code for this driver can be found at https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/i2c/busses.
graph TD;
A[i2c-core-base]-->B[i2c_designware_core];
B[i2c_designware_core]-->C[i2c_designware_master]
C[i2c_designware_master]-->E[i2c_designware_slave]Driver Capabilities¶
- Manage the communication for I2C Master buses as well as Slave.
- Handle the data transfer between connected devices over the I2C bus.
Kernel Configurations¶
CONFIG_I2C_DESIGNWARE_CORE
CONFIG_I2C_DESIGNWARE_SLAVE
Device Tree¶
Example Device tree location to configure the i2c:
Known Issues¶
None Known
Notices & Disclaimers¶
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Created: May 25, 2024