Zephyr Drivers¶
The table below provides a comprehensive list of embedded Zephyr drivers available for the HPS and Nios V on Agilex 5 FPGA devices.
- IP Name column indicates what type of IP the driver targets.
- Target is
- Documentation column provides a link to driver description, architectural details, driver capabilities and configurations, known issues and release information.
- Upstream Status column indicates mainstream status of driver.
- Kernel Source indicates location of driver.
You can use the filter fields to narrow your search.
| IP Name | Supported Device(s) | Target | Documentation | Upstream Status | Kernel Source |
|---|---|---|---|---|---|
| Clock Manager | Agilex 5 | HPS | Clock Manager | Yes | clock_control_agilex5 |
| Cold & Warm Reset -Power State Coordination Interface (PSCI) | Agilex 5 | HPS | PSCI | Yes | pm_cpu_ops_psci |
| DMA Controller | Agilex 5 | HPS | DMAC | Yes | dma |
| General Purpose Timer | Agilex 5 | HPS | Timer | Yes | counter_dw_timer |
| GPIO | Agilex 5 | HPS | gpio | No | gpio_intel_socfpga |
| QSPI | Agilex 5 | HPS | QSPI | Yes | flash_cadence_qspi_nor |
| Reset Manager | Agilex 5 | HPS | Reset Manager | Yes | reset_intel_socfpga |
| Single Event Upset (SEU) | Agilex 5 | HPS | SEU | In Progress | pull/67097 |
| SMP | Agilex 5 | HPS | SMP | Yes | smp |
| UART | Agilex 5 | HPS | UART | Yes | uart_ns16550 |
| Watchdog Timer | Agilex 5 | HPS | Watchdog Timer | Yes | wdt_dw |
Last update:
December 19, 2024
Created: August 7, 2024
Created: August 7, 2024