Drive-On-Chip with Functional Safety Design Example for Agilex™ 5 Devices¶

Overview¶

This design demonstrates how to achieve IEC 61508 SIL 2 and ISO 13849 Cat 3 PLd safety certification using Agilex™ 5 SoC devices. The design is based on the TÜV Rheinland approved Intel® Cyclone V SoC FPGA Cat 3 PLd and SIL 2 safety concept.

Altera® does not intend you to certify the design. Therefore, Altera® only applies the safety design process described in IEC 61508 only where relevant. The design shows how you apply the Altera® SoC FPGA Cat 3 PL d and SIL 2 safety concept. The architecture is based around a particular component of the drive-on-chip, the speed limit. You can extend the concept to monitor, cross-compare, and control other relevant physical and logical variables that are key for safety.

This design demonstrates synchronous control of up to two three-phase permanent magnet synchronous motors (PMSMs) or brushless DC (BLDC) motors. The design includes a motor and power board model that removes the need for a physical motor setup. This design is an extension of the existing Drive-on-Chip Design Example for Agilex™ 5 Devices. It includes safety function to demonstrate how Agilex™ 5 SoC devices may achieve IEC 61508 SIL 2 or ISO 13849 Cat 3 PL d safety certification.

You need an Altera® Agilex™ 5 FPGA E-Series 065B Modular Development Kit to run the design. The motor and power model helps you tune and test the control system before using a physical power stage. The motor and power board model are based on the former Tandem Motion 48 V board, described in AN 994 Drive-on-Chip Design Example for Agilex™ 7 Devices.

High-Level Block Diagram of the Drive-On-Chip
with Functional Safety Design Example.

The blocks in yellow belong to the original Drive-On-Chip Design Example for ™ 5 Devices. The blocks in green are the implementation of the FPGA safety channel and the blue blocks are the implementation of the HPS safety channel. The diagram shows the logic that the design shares between both channels necessary to process the safety response time (1ms) and for data sharing for cross-comparison.

The following diagrams provide an overview of the interaction of software and hardware components in this example design.

High-Level HW/SW Block Diagram of the Drive-On-Chip
with Functional Safety Design Example.

Pre-requisites¶

Software Requirements to run¶

The following are required to be able to fully exercise the Agilex™ 5 Modular Development Kit:

Host PC with
- 64 GB of RAM. Less will be fine for only exercising the binaries, and not rebuilding.
- Linux/Windows OS installed.
- Serial terminal (for example GtkTerm or Minicom on Linux and TeraTerm or PuTTY on Windows)
- Tool to write images for USB sticks or SD cards such as DiskImager or Rufus
- Altera® Quartus® Prime Pro Edition Version 24.3
- To run the GUI:
  - Python 3.10.5
  - Pip 22.2.2
  - Python libraries: Pyside6 (6.3.2), pyqtgraph (0.13.1), numpy (1.23.2), Python Standard Libraries: traceback, sys, re, math, struct, subprocess, os, time, threading.

Software Requirements to build¶

62 GB free storage (~2GB for Quartus® Build and ~60GB for YOCTO/KAS build)
Python/PIP/KAS for Yocto Build (or a suitable container).
FPGA NiosV/g Open-Source Tools 24.3 (installed with Quartus® Prime).
Altera® Quartus® Agilex™ 5 Support
MATLAB 2021b with Simulink (Optional).
DSP Builder for Altera® FPGAs Pro Edition v24.3 (Optional).

Hardware Requirements¶

Altera® Agilex™; 5 FPGA E-Series 065B Modular Development Kit, ordering code MK-A5E065BB32AES1. Refer to Agilex™ 5 FPGA E-Series 065B Modular Development Kit for more information about the development kit.
Power supply
2 x Micro USB Cable
Ethernet Cable (optional)
Micro SD card and USB card writer

Optional:
- Motor and power board

Agilex™ 5 FPGA E-Series 065B Modular Development Kit.

Sources¶

The sources provided in this table are the latest and greatest recommended for Quartus® 24.3 builds. It is recommended to the user to use updated version of the building blocks for production environments. This is an example design not ready for production or end-production.

Example Design Source Repositories.

Component	Location	Branch
Assets Release Tag	https://github.com/altera-fpga/agilex-ed-drive-on-chip/releases/tag/rel-safety-24.3	rel-safety-24.3
Drive-On-Chip Variants	https://github.com/altera-fpga/agilex-ed-drive-on-chip	rel/24.1
Modular Design Toolkit	https://github.com/altera-fpga/modular-design-toolkit	re/24.1
Linux	https://github.com/altera-opensource/linux-socfpga	socfpga-6.6.22-lts
Arm Trusted Firmware	https://github.com/ARM-software/arm-trusted-firmware	socfpga_v2.11.0
U-Boot	https://github.com/altera-opensource/u-boot-socfpga	v2024.01
Yocto Project: poky	https://git.yoctoproject.org/poky	scarthgap
Yocto Project: meta-intel-fpga	https://git.yoctoproject.org/meta-intel-fpga	scarthgap

Getting Started - run with pre-build binaries¶

Follow the instructions provided in this section to run this example design in Agilex™ 5 FPGA E-Series 065B Modular Development Kit.

Download the minimum Pre-built Binaries¶

Download the Agilex™ 5 Modular Development Kit binaries that are located at:

Binaries

Boot Source	Link
SD Card	core-image-minimal-agilex5_modular.rootfs.wic
QSPI	top.hps.jic
GUI	doc-gui.zip

Setting Up your Development Board¶

Configure the board switches: The following provides the default configuration for all the switches in the board.

Development Board switch position.

Main configurations used in this example design

JTAG: SOM SW4[2:1]=OFF:OFF
ASx4 (QSPI): SOM SW4[2:1]=ON:ON

Connect micro USB cable from bottom left of the carrier board to PC (J35). This will be used for JTAG communication. Look at what ports are enumerated on your host computer, there should be a series of four. (See the figure bellow).
Connect micro USB cable from bottom right of the SOM board to PC (J2, HSP_UART). This will be used for HPS UART communication. Look at what ports are enumerated on your host computer, there should be a series of four. Use the 3^rd one in the list as the HPS serial port.(See the figure bellow).

USB connections to the board.

Burn the SD card image.¶

Download SD card image from the "prebuilt binaries" (<name>.wic).
Write the <name>.wic. SD card image to the micro SD card using the included USB writer in the host computer:
- On Linux, use the dd utility as shown next:
```
# Determine the device asociated with the SD card on the host computer. 
cat /proc/partitions
# This will return for example /dev/sd<x>
# Use dd to write the image in the corresponding device
sudo dd if=<name>.wic of=/dev/sd<x> bs=1M
# Flush the changes to the SD card
sync
```
- On Windows, use the Win32DiskImager program, available at https://sourceforge.net/projects/win32diskimager. For this, first rename the .wic to an .img file (sdcard.img for example) and write the image as shown in the next figure:
Write an SD card using "Disk Imager" tool.

Turn off the board and insert the SD card in the micro SD card slot in the SOM board.

Program the QSPI Flash Memory.¶

To Write/Program QSPI Flash

a. Power down board. Set MSEL dipswitch S4 on SOM to JTAG: OFF-OFF

b. Power up the board.

c. Download the JIC image, then write it to QSPI with the command. (Optional: Use the Quartus® Programmer GUI)
```
quartus_pgm -c 1 -m jtag -o "pvi;top.hps.jic" 
```
d. (Optional) Use the Quartus® Programmer GUI:
- Launch the Quartus® Programmer and Configure the "Hardware Setup..." settings as following:
Programmer GUI Hardware Settings.
- Click "Auto Detect", select the device A5EC065BB32AR0 and press "Change File.."
Programmer after "Auto Detect".
- Select your top.hps.jic (or equivalent). The MT25QU02G device should show. Select the "Program/Configure" box, and press "Start" button. Wait until completed (It could take several minutes.)
Programming the QSPI Flash with JIC file.

Power down the board. Set MSEL dip switch S4 on SOM to ASX4 (QSPI): ON-ON

Run the design example¶

Power up the board and setup the serial terminal (minicom, putty, etc):
- Select the correct COMx port. From the HPS serial UART, select the third port (out of four).
- Serial Port configuration:
  - Baud rate: 115200, Data bits: 8, Stop bits: 1, CRC: disabled, Hardware flow control: disabled
- Connect your terminal emulator.

Wait for Linux to boot, the safety application should run after ~30s. (No inputs from the user required)

The serial terminal should show the following:

HPS Safety Function Serial Port Printing.

Keep the Altera® FPGA download cable and JTAG connection to the board.

Debugging and Monitoring the Safety Function.¶

Unzip the GUI source code:

    unzip doc-gui_1.0.0.zip
    cd <download>/doc-gui_1.0.0

Open a terminal and run:

    python __main__.py

Select the right JTAG master from the menu (if it is not selected automatically). Usually AE5(C0…0)...

Select the Agilex™ device in the JTAG Device dropdown menu.

When the GUI is running, change to the Safety tab, in the left panel, with the ! symbol. The tab summarizes of the safety status of the design.The Safety tab shows information about the status of both safety channels, FPGA and HPS. The estimated speed, the payload comparison results, the over-speed detection and the payload count. The Status widget shows if the motor goes into safe state.

Safety Function Tab.

Looking into the Drive-On-Chip Output.¶

Additionally, just after few seconds fromt turning the board on, you can observe the output from the drive-on-chip application that runs in the Nios V/g processor.

Connect a micro-USB cable to the integrated USB blaster II in the board.
Run (source the Nios V command shell if required):

  juart-terminal -d 2 -i 0

Nios V/g Drive-on-chip application output.

Recommended User Flows¶

Using resources available you can build, compile, modify and run this design example. There are 2 additional user flows that can be exercised

User Flow 1: Getting Started - Running with pre-build binaries.
User Flow 2: Running the example design using the QAR and KAS
User Flow 3: Running the example design by create/build Modular Design Toolkit (MDT) and KAS.

More resources.

Source	Link
Pre-created QAR file	DOC_SAFETY_TANDEM_MOTORSIM_AGILEX5.qar
JIC/RBF files	top.hps.jic top.core.rbf
u-boot-spl-dtb.hex	u-boot-spl-dtb.hex
HPS Channel Safety Application	hpssafechannel_1.0.tar.gz

Recommended User Flows.

User Flow	Description	User flow 1	User flow 2	User flow 3
Pre-requisites	Software Requirements to run.	✓	✓	✓
	Software Requirements to build.	✗	✓	✓
	Hardware Requirements.	✓	✓	✓
	Download the minimum Pre-built Binaries.	✓	✗	✗
HW-Compilation	Compile pre-created QAR with Quartus®.	✗	✓	✗
	Generating and Building the NiosV/g BSP for the Drive-On-Chip Application.	✗	✓	✗
	Creating and Building the Design based on Modular Design Toolkit (MDT).	✗	✗	✓
	Creating the QSPI Flash and SD card configuration bitstreams for the board (JIC/RBF).	✗	✓	✓
SW-Compilation	Create SD card image (.wic) using YOCTO/KAS NOTE: use KAS_MACHINE=agilex5_modular and kas-safety_dual_axis.yml configuration	✗	✓	✓
Programming	Setting Up your Development Board.	✓	✓	✓
	Burn the SD card image.	✓	✓	✓
	Program the QSPI Flash Memory.	✓	✓	✓
Testing	Run the example design.	✓	✓	✓
	Debugging and Monitoring the Safety Function.	✓	✓	✓
	Looking into the Drive-On-Chip Output.	✓	✓	✓