Drive-On-Chip with Functional Safety Design Example for Agilex™ 5 Devices¶
Acronyms and Terminology
Term | Description |
---|---|
DoC | Drive On Chip |
FOC | Field Oriented Control |
QEP | Quadrature Encoder Pulse |
EMIF | External Memory Interface |
FPGA | Field Programmable Gate Array |
BSP | Board Support Package |
IP | Intellectual Property (hardware) |
DSP | Digital Signal Processing |
CAN | Controller Area Network |
GUI | Graphical User Interface |
JTAG | Joint Test Action Group (industry standard for testing) |
UART | Universal Asynchronous Receiver-Transmitter |
RAM | Random Access Memory |
SRT | Safety Response Time |
HPS | Hard Processor System |
ESL | External Safety Logic |
FUSA | Functional Safety |
APB | Advance Peripheral Bus Interface |
AXI | Advance eXtensible Interface bus protocol |
SDM | Secure Device Manager |
ADC | Analog to Digital Converter |
HPS2FPGA | Hard Processor System to FPGA, usually referring to a hardened memory-mapped bridge |
IRQ | Interrupt Request |
PD | Usually used to refer to "Platform Designer |
SPI | Serial Peripheral Interface |
PIO | Parallel Input/Output |
DSP BA | Used to refer to "DSP Builder Advanced tool |
RTL | Register Transfer Level |
DTS | Device Tree Source |
DTB | Device Tree Blob |
Last update:
March 6, 2025
Created: March 6, 2025
Created: March 6, 2025