Clock Manager Driver for Hard Processor System¶
Last updated: December 19, 2024
Upstream Status: No
Devices supported: Agilex 5
Introduction¶
Hard Processor System (HPS) clock generation is centralized in the clock manager. The clock manager is responsible for providing software-programmable clock control to configure all clocks generated in the HPS. Clocks are organized into clock groups.
A clock group is a set of clock signals that originate from the same clock source which may be synchronous to each other. The Clock Manager has a two Phase-Locked Loop (PLL) clock group where the clock source is a common PLL voltage-controlled oscillator (VCO). A clock group which is independent and asynchronous to other clocks may only have a single clock, also known as clock slice. Peripheral clocks are a group of independent clock slices.
For more information please refer to the Intel Agilex 5 Hard Processor System Technical Reference Manual.
Features¶
- Generates and manages clocks in the HPS.
- Contains two flexible PLL blocks Main PLL and Peripheral PLL.
- Generates clock gate controls for enabling and disabling most of the clocks.
- Allows software to program clock characteristics.
- Supports interrupting the Cortex-A53 MPCore on PLL-lock and loss-of-lock.
Driver Sources¶
The source code for this driver can be found at https://github.com/altera-opensource/linux-socfpga/blob/socfpga-6.1.55-lts/drivers/clk/socfpga/clk-agilex5.c.
Driver Capabilities¶
- Support to configure peripherals clock through common clock framework.
- Support to enable or disable software-managed clocks.
Kernel Configurations¶
CONFIG_CLK_INTEL_SOCFPGA64
Device Tree¶
Example Device tree location:
Also dt-bindings can be found at:
Known Issues¶
None known
Notices & Disclaimers¶
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Created: May 25, 2024