Interrupt controller (GICv3) Driver for Hard Processor System¶
Last updated: December 19, 2024
Upstream Status: Upstreamed
Devices supported: Agilex 5
Introduction¶
The interrupt controller driver handles general initialization of the interrupt controller in the HPS.
The Arm® Generic Interrupt Controller (GIC) handles interrupts from peripherals to the cores and between cores. To find out more about the features and functions of the GIC controller, please refer to Agilex 5 Hard Processor System Technical Reference Manual
Driver Sources¶
The source code for this driver can be found at:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/irqchip/irq-gic-v3.c
Driver Capabilities¶
- Initialize and configure the GICv3 interrupt controller hardware during system boot-up.
- Handles interrupts generated by various sources in the system.
- Routes interrupt from their sources to the appropriate CPU cores.
- Provides generic API to manage interrupts.
- Support distributed interrupts across multiple GIC instances.
Kernel Configurations¶
CONFIG_ARM_GIC_V3
CONFIG_ARM_GIC_V3_ITS
Device Tree¶
Example Device tree location to configure the irq_gic_v3:
Known Issues¶
None Known
Notices & Disclaimers¶
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Created: May 25, 2024