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HPS TSN SGMII XCVR System 3x2.5G Example Design User Guide

Introduction

The IEEE Ethernet is a core technology which is a backbone for IT operations and was designed to provide best effort communication suitable for IT operations. Operational Technology vendors have innovatively used Core IEEE Ethernet technology with proprietary solutions for enabling time-bounded communication. To address the need for precision timing, traffic shaping, and time-bounded communication over networks, IEEE introduced a suite of standards known as Time Sensitive Networking (TSN).

Agilex™ 5 E-Series is designed as an end point for Industrial automation application with support for the following TSN protocols:

Time Synchronization Protocols:
  • IEEE 1588-2008 Advanced Timestamp (Precision Time Protocol - PTP):
    • Function: Provides sub-microsecond accuracy for time synchronization between computing systems over a local area network.
      • Key Features: 2-step synchronization, PTP offload, and timestamping.
      • Use Case: Synchronizing industrial devices to operate in unison, ensuring coordinated actions across factory or plant operations.
    • IEEE 802.1AS (Timing and Synchronization):
      • Function: A profile of PTP (version 2) that ensures precise time synchronization in a hierarchical master-slave architecture.
      • Key Features: Prioritizes accuracy and variability of timing, crucial for industrial and automotive systems.
      • Use Case: Synchronizing devices to a common time for optimal operation and collaboration.
Credit Based Shaper Protocol:
  • IEEE 802.1Qav (Time-Sensitive Streams Forwarding and Queuing):
    • Function: Provides low-latency, time-synchronized delivery of audio and video streams over Ethernet networks.
      • Key Features: Credit-based shaper ensuring end-to-end guaranteed bandwidth with fairness to best-effort traffic.
      • Use Case: Ensuring dedicated bandwidth for audio-video bridging (AVB) streams with minimal latency.
Traffic Scheduling Protocols:
  • IEEE 802.1Qbv (Time-Scheduled Traffic Enhancements):
    • Function: Enables the transmission of frames at specific scheduled times within microsecond ranges.
      • Key Features: Critical for time-sensitive scheduled traffic in industrial applications.
      • Use Case: Facilitating precise, time-critical communication for industrial devices like PLCs and drives.
    • IEEE 802.1Qbu (Frame Preemption):
      • Function: Allows high-priority frames to preempt lower-priority frames, reducing latency and jitter.
      • Key Features: Utilizes Express Media Access Control (eMAC) and Preemptable Media Access Control (pMAC).
      • Use Case: Ensuring high-priority frames arrive with fixed latency, crucial for applications requiring consistent timing.

These TSN standards collectively enable precise timing, traffic shaping, and time-bounded communication, making them indispensable for applications requiring high reliability and determinism.

The details of TSN is not in the scope of this document. Here are some reference to the TSN specifications:

TSN SGMII+ XCVR 3x2.5G Overview

The TSN SGMII+ XCVR is a Reference design, enable datapath between HPS, EMAC Controller, Multirate Ethernet PHY IP and Marvell PHY 88E2110 running at 2.5G rate on the Agilex™ 5 FPGA E-Series 065B Modular Development Kit.

Note:              
 1. This is the pre-production release of the Agilex™ 5 TSN SGMII XCVR System Example Design, on Agilex™ 5 FPGA E-Series 065B Modular Development Kit with -6S speed grade. This corresponds to Engineering Samples Silicon quality.
 2. Three PHY is enabled with 2.5G fixed rate in this release.

Prerequisites

  • Agilex™ 5 FPGA E-Series 065B Modular Development Kit, ordering code MK-A5E065BB32AES1. Refer to the board documentation for more information about the development kit.
  • Mini and Micro USB Cable. Included with the development kit.
  • CAT6A Ethernet Cable. Included with the development kit.
  • Micro SD card and USB card writer. Included with the development kit.
  • Host PC with 64 GB of RAM. Less will be fine for only exercising the binaries, and not rebuilding the GSRD.
  • Linux OS installed on host PC, preferably Ubuntu 22.04LTS , while other versions and distributions may work too.
  • Serial terminal (for example GtkTerm or Minicom on Linux and TeraTerm or PuTTY on Windows)
  • Quartus® Prime Pro Edition software version 25.1.1 is used to recompile the hardware design. If only writing binaries is required, then the Quartus® Prime Pro Edition Programmer version 25.1.1 is sufficient.
  • Local Ethernet network, with DHCP server Internet connection. For downloading the files, especially when rebuilding the GSRD.

Release Contents

Binaries

  • Prebuilt binaries are located here.

Sources

Altera® Quartus® Prime Pro Edition Version 25.1.1 and the following software component versions integrate the 25.1.1 release.

Note: Regarding the GHRD components in the following table, only the device-specific GHRD is used in this page.

Component Location Branch Commit ID/Tag
Agilex 5 GHRD https://github.com/altera-fpga/agilex5-ed-tsn-sgmii/tree/25.1.1-1/src/hw rel/25.1.1 rel/25.1.1
Linux https://github.com/altera-fpga/linux-socfpga socfpga-6.12.19-lts QPDS25.1.1_REL_GSRD_PR
Arm Trusted Firmware https://github.com/altera-fpga/arm-trusted-firmware socfpga_v2.12.1 QPDS25.1.1_REL_GSRD_PR
U-Boot https://github.com/altera-fpga/u-boot-socfpga socfpga_v2025.04 QPDS25.1.1_REL_GSRD_PR
Yocto Project https://git.yoctoproject.org/poky walnascar latest
Yocto Project: meta-intel-fpga https://git.yoctoproject.org/meta-intel-fpga walnascar QPDS25.1.1_REL_GSRD_PR
Yocto Project: meta-intel-fpga-refdes https://github.com/altera-fpga/meta-intel-fpga-refdes walnascar QPDS25.1.1_REL_GSRD_PR
GSRD Build Script: gsrd-socfpga https://github.com/altera-fpga/agilex5-ed-tsn-sgmii/tree/25.1.1-1/src/sw rel/25.1.1 rel/25.1.1

Note: The combination of the component versions indicated in the table above has been validated through the use cases described in this page and it is strongly recommended to use these versions together. If you decided to use any component with different version than the indicated, there is not warranty that this will work.

Release Notes

TSN XCVR SGMII+ 2.5G Architecture

Agilex™ FPGAs provide a powerful platform for showcasing 2.5G Ethernet with TSN-enabled applications with all the TSN features including IEEE 802.1AS, IEEE802.1Qbv, IEEE802.1Qbu, IEEE802.1Qav in HPS subsystem by enabling the EMAC Controller. To support the 2.5G rate, you must enable the 8-bit GMII interface to the FPGA fabric, from where it gets connected to a Marvell PHY 88E2110 (through the FPGA transceivers) device to drive the RJ45 CAT6A copper media.

This design demonstrate 3x2.5G ports to HPS

Enable the Data path between HPS <-> XGMAC <->MR PHY (Direct mode) <-> 2 Marvell PHY port + 1 SFP running at 2.5G rate.

This Example design showcases 2.5G data rate.

  • Enable the Deterministic Latency (DL) feature of MR PHY IP which precisely determines the delay between the PCS elastic FIFO (EFIFO) and the PMA pins for TSN usecases. Also enable the CSR interface with HPS Light weight bridge to convey these delays (Soft PCS, Hard PCS and PMA delays) for both RX and TX directions.
  • GMII (8-bit) interface for TSN enabled ethernet data transfers to and from XGMAC to external PHY. Tranceiever’s reference clocks are used to derive the required frequency for running this parallel interface as the expectation is to have zero ppm difference between these clocks.

HPS Subsystem

The Hard Processor System (HPS) in this design is a critical component that interfaces with various subsystems and peripherals to ensure efficient and high-performance operation. The following are the key connections of the HPS to other design components;

  • Light Weight HPS to FPGA Manager (H2F) interface to access control and status registers of TSN Subsystem and Peripheral Subsystem
  • 8-bit EMAC GMII interface to connect to 1G/2.5G/5G/10G Multirate Ethernet PHY IP for TSN-enabled ethernet data transfers

TSN Subsystem

The main components of the TSN Subsystem are Multirate Ethernet PHY IP, GTS System PLL Clocks IP, Reset Release IP and IOPLL IP.

  • The Multirate Ethernet PHY IP transmits outgoing traffic (from HPS GMII interface) and receives incoming traffic through GTS Transceiver PHY.
  • The GMII adapter is enabled to convert the 8-bit GMII data from HPS to the 16-bit data inside the Multirate Ethernet PHY IP
  • The IEEE 1588 Precision Time Protocol feature is enabled to accurately measure internal data path delay, ensuring high accuracy of TSN applications.
  • The GTS System PLL Clocks IP provides a system PLL clock input to Multirate Ethernet PHY IP, while the IOPLL IP generates a clock source for latency_sclk and latency_measurement_clk of Multirate Ethernet PHY IP.

Hardware Setup

The Board-to-Board hardware setup connection details are captured in the image below.

Note:

1. This is the reference hardware setup and user can leverage with their own hardware setup(Ex: Board to Third party device).

Address Map Details

HPS LW H2F Register Map

Address Offset Size (Bytes) Peripheral Description
GHRD-aligned address space
0x2001_0000 8 System ID Hardware configuration system ID (0xacd5cafe)
0x2001_0060 16 Button PIO Push Button
0x2001_0070 16 DIPSW PIO DIP Switch
0x2001_0080 16 LED PIO LED connections on board
Application-specific address space
0x3002_0100 64 Multirate Ethernet PHY Multirate Ethernet PHY IP CSR
0x3002_0180 64 Multirate Ethernet PHY Multirate Ethernet PHY IP CSR
0x3002_0200 64 Multirate Ethernet PHY Multirate Ethernet PHY IP CSR
0x2002_0300 256 User space CSR Sideband status and control signals of various modules

User Space CSR

The User Space CSR contains registers specific to system-level status (e.g. PLL locked, RX ready) and control (e.g., reset).

Access Definition
RO Read only
RW Read and write
Multirate Ethernet PHY Status Register (Offset 0x00)
Name Bit Access Default Description
Reserved [31:21] RO 11'b0 Reserved
PHY_2_op_speed [20:18] RO 3'b100 PHY2 -MRPHY Op speed - 2.5G
PHY_2_rx_block_lock [17:17] RO 1'b0 PHY2 -Asserted when 66b block alignment is finished on all PCS virtual lanes
PHY_2_tx_ready [16:16] RO 1'b0 PHY2 -Asserted when MRPHY TX is ready
PHY_2_rx_ready [15:15] RO 1'b0 PHY2 -Asserted when MRPHY RX is ready
PHY_2_mrphy_pll_lock [14:14] RO 1'b0 PHY2 -Asserted when PLL in MRPHY soft logic is locked
PHY_1_op_speed [13:11] RO 3'b100 PHY1 -MRPHY Op speed - 2.5G
PHY_1_rx_block_lock [10:10] RO 1'b0 PHY1 -Asserted when 66b block alignment is finished on all PCS virtual lanes
PHY_1_tx_ready [9:9] RO 1'b0 PHY1 -Asserted when MRPHY TX is ready
PHY_1_rx_ready [8:8] RO 1'b0 PHY1 -Asserted when MRPHY RX is ready
PHY_1_mrphy_pll_lock [7:7] RO 1'b0 PHY1 -Asserted when PLL in MRPHY soft logic is locked
PHY_0_op_speed [6:4] RO 3'b100 PHY0 -MRPHY Op speed - 2.5G
PHY_0_rx_block_lock [3:3] RO 1'b0 PHY0 -Asserted when 66b block alignment is finished on all PCS virtual lanes
PHY_0_tx_ready [2:2] RO 1'b0 PHY0 -Asserted when MRPHY TX is ready
PHY_0_rx_ready [1:1] RO 1'b0 PHY0 -Asserted when MRPHY RX is ready
PHY_0_mrphy_pll_lock [0:0] RO 1'b0 PHY0 - Asserted when PLL in MRPHY soft logic is locked
Multirate Ethernet PHY Reset Control Register (Offset 0x04)
Name Bit Access Default Description
Reserved [31:9] RO 23'b0 Reserved
PHY_2_i_rx_rst_n [8:8] RW 1'b1 PHY2 -Reset MRPHY RX path. Self cleared on o_rx_rst_ack_n
PHY_2_i_tx_rst_n [7:7] RW 1'b1 PHY2 -Reset MRPHY TX path. Self cleared on o_rx_rst_ack_n
PHY_2_i_rst_n [6:6] RW 1'b1 PHY2 -Global reset to MRPHY. Self cleared on o_rst_ack_n
PHY_1_i_rx_rst_n [5:5] RW 1'b1 PHY1 -Reset MRPHY RX path. Self cleared on o_rx_rst_ack_n
PHY_1_i_tx_rst_n [4:4] RW 1'b1 PHY1 -Reset MRPHY TX path. Self cleared on o_rx_rst_ack_n
PHY_1_i_rst_n [3:3] RW 1'b1 PHY1 -Global reset to MRPHY. Self cleared on o_rst_ack_n
PHY_0_i_rx_rst_n [2:2] RW 1'b1 PHY0 -Reset MRPHY RX path. Self cleared on o_rx_rst_ack_n
PHY_0_i_tx_rst_n [1:1] RW 1'b1 PHY0 -Reset MRPHY TX path. Self cleared on o_rx_rst_ack_n
PHY_0_i_rst_n [0:0] RW 1'b1 PHY0 -Global reset to MRPHY. Self cleared on o_rst_ack_n
TX Delay Register (Offset 0x08)
Name Bit Access Default Description
Reserved [31:12] RO 20'b0 Reserved
Additional_User_added_delay1 [11:8] RO 4'b0 Future - In concurrent use case
Additional_User_added_delay2 [7:4] RO 4'b0 Future - In concurrent use case
Additional_User_added_delay3 [3:0] RO 4'b0 Additional GMII Datapath Delay added by used if timing issue arise in number of clock cycles gmii8_tx_clkout
RX Delay Register (Offset 0x0C)
Name Bit Access Default Description
Reserved [31:12] RO 20'b0 Reserved
Additional_User_added_delay1 [11:8] RO 4'b0 Future - In concurrent use case
Additional_User_added_delay2 [7:4] RO 4'b0 Future - In concurrent use case
Additional_User_added_delay3 [3:0] RO 4'b0 Additional GMII Datapath Delay added by used if timing issue arise in number of clock cycles gmii8_rx_clkout
Error Status Register (Offset 0x10)
Name Bit Access Default Description
Reserved [31:3] RO 29'b0 Reserved
Unsupported_Speed_Error1 [2:1] RW 2'b0 For concurrent Usecases
Unsupported_Speed_Error2 [0:0] RW 1'b0 Assert high when XGMAC publish unsupported speeds. SW to clear these bits once addressed

User Flow

There are two ways to test the design based on user flow.

User Flow 1: Testing with Prebuild Binaries.
User Flow 2: Testing Complete Flow.
User Flow Description Required for User flow 1 Required for User flow 2
Environment Setup Tools Download and Installation Yes Yes
Installing Dependency Packages for SW Compilation No Yes
Package Download No Yes
Compilation Simulation No No
Hardware Compilation No Yes
Software Compilation No Yes
Programing Programing Hardware binary Yes Yes
Programing Software Image Yes Yes
Linux boot Yes Yes
Testing Run Ping Test Yes Yes
Running iperf Test Yes Yes

Environment Setup

Tools Download and Installation

1. Quartus Prime Pro

  • Download the Quartus® Prime Pro Edition software version 25.1.1 from the FPGA Software Download Center webpage of the Intel website. Follow the on-screen instructions to complete the installation process. Choose an installation directory that is relative to the Quartus® Prime Pro Edition software installation directory.
  • Set up the Quartus tools in the PATH, so they are accessible without full path.
    export QUARTUS_ROOTDIR=~/altera_pro/25.1.1/quartus/
    export PATH=$QUARTUS_ROOTDIR/bin:$QUARTUS_ROOTDIR/linux64:$QUARTUS_ROOTDIR/../qsys/bin:$PATH

2. Download and setup the build toolchain. It will be used only by the GHRD makefile to build the debug HPS FSBL, to build the _hps_debug.sof file:

Note that this is installed in the TOP_FOLDER. You may installed this is in other location, but note the path and export it accordingly

# Create the top folder to store all the build artifacts:
sudo rm -rf artifacts.enablement
mkdir artifacts.enablement
cd artifacts.enablement
export TOP_FOLDER=`pwd`

cd $TOP_FOLDER
wget https://developer.arm.com/-/media/Files/downloads/gnu/11.2-2022.02/binrel\
/gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
tar xf gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
rm -f gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz

export PATH=`pwd`/gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu/bin:$PATH
export ARCH=arm64
export CROSS_COMPILE=aarch64-none-linux-gnu-

3. Win32 Disk Imager

4. Agile™ 5 FPGA E-Series 065B Modular Development Kit Board Test System (BTS)

Installing Dependency Packages for SW Compilation

Follow the instructions in the Base GSRD Yocto Build Prerequisites section.

Package Download

cd $TOP_FOLDER
rm -rf agilex5-ed-tsn-sgmii
git clone -b rel/25.1.1 https://github.com/altera-fpga/agilex5-ed-tsn-sgmii

Compilation

Hardware Compilation

cd $TOP_FOLDER/agilex5-ed-tsn-sgmii/src/hw/a5e065bb32aes1_mdk_3x2.5G/
quartus_sh --flow compile a5ed065bb32ae6sr0

The following file will be generated:

$TOP_FOLDER/agilex5-ed-tsn-sgmii/src/hw/a5e065bb32aes1_mdk_3x2.5G/output_files/a5ed065bb32ae6sr0.sof

Build QSPI Image
cd $TOP_FOLDER
rm -f a5ed065bb32ae6sr0.hps.jic a5ed065bb32ae6sr0.core.rbf

# Note : If user doing compilation first time, download the prebuilt u-boot-spl-dtb.hex  file and create the following path $TOP_FOLDER/agilex5-ed-tsn-sgmii/src/sw/agilex5_mk_a5e065bb32aes1-gsrd-images/u-boot-agilex5-socdk-gsrd-atf/ and copy the u boot file here.

quartus_pfg \
-c agilex5-ed-tsn-sgmii/src/hw/a5e065bb32aes1_mdk_3x2.5G/output_files/a5ed065bb32ae6sr0.sof a5ed065bb32ae6sr0.jic \
-o device=MT25QU02G \
-o flash_loader=A5ED065BB32AE6SR0 \
-o hps_path=agilex5-ed-tsn-sgmii/src/sw/agilex5_mk_a5e065bb32aes1-gsrd-images/u-boot-agilex5-socdk-gsrd-atf/u-boot-spl-dtb.hex \
-o mode=ASX4 \
-o hps=1

The following file will be created:

$TOP_FOLDER/a5ed065bb32ae6sr0.jic

Build RBF
cd $TOP_FOLDER
rm -f a5ed065bb32ae6sr0.*.rbf

# Note : If user doing compilation first time, download the prebuilt u-boot-spl-dtb.hex  file and create the following path $TOP_FOLDER/agilex5-ed-tsn-sgmii/src/sw/agilex5_mk_a5e065bb32aes1-gsrd-images/u-boot-agilex5-socdk-gsrd-atf/ and copy the u boot file here.

quartus_pfg \
-c agilex5-ed-tsn-sgmii/src/hw/a5e065bb32aes1_mdk_3x2.5G/output_files/a5ed065bb32ae6sr0.sof  a5ed065bb32ae6sr0.rbf \
-o hps_path=agilex5-ed-tsn-sgmii/src/sw/agilex5_mk_a5e065bb32aes1-gsrd-images/u-boot-agilex5-socdk-gsrd-atf/u-boot-spl-dtb.hex \
-o hps=1

The following file will be generated:

$TOP_FOLDER/ghrd_a5ed065bb32ae6sr0.core.rbf $TOP_FOLDER/ghrd_a5ed065bb32ae6sr0.hps.rbf

Software Compilation

Set Up Yocto
   cd $TOP_FOLDER/agilex5-ed-tsn-sgmii/src/sw
   # Run the `agilex5_mk_a5e065bb32aes1-gsrd-build.sh` script to sync the submodules.
   . agilex5_mk_a5e065bb32aes1-gsrd-build.sh
   # Run the `build_setup` script to set up the build environment.
   build_setup
Optional: Follow these steps, if you have a custom GHRD

Follow the below procedure to add the generated agilex5_*_a5e065bb32aes1_gsrd_ghrd.core.rbf file.

  • For Agilex5 MK-A5E065BB32AES1:-agilex5_mk_a5e065bb32aes1_gsrd_ghrd.core.rbf

Update the recipe $WORKSPACE/meta-sm-tsn-sgmii/recipes-bsp/ghrd/hw-ref-design.bbappend as follows:

cd $TOP_FOLDER
CORE_RBF=$WORKSPACE/meta-sm-tsn-sgmii/recipes-bsp/ghrd/files/agilex5_mk_a5e065bb32aes1_gsrd_ghrd.core.rbf
rm -rf $CORE_RBF
ln -s $TOP_FOLDER/ghrd_a5ed065bb32ae6sr0.core.rbf $CORE_RBF
CORE_SHA=$(sha256sum $CORE_RBF | cut -f1 -d" ")
FILE="$WORKSPACE/meta-sm-tsn-sgmii/recipes-bsp/ghrd/hw-ref-design.bbappend"
OLD_URI='SRC_URI\[agilex5_mk_a5e065bb32aes1_gsrd_core_cfg3.sha256sum\] += "[^"]*"'
NEW_URI="SRC_URI[agilex5_mk_a5e065bb32aes1_gsrd_core_cfg3.sha256sum] += \"$CORE_SHA\""
sed -i "s|$OLD_URI|$NEW_URI|" "$FILE"
Build Yocto

Build Yocto:

    # Run the `bitbake_image` command to generate the binaries.
    bitbake_image

Gather Files:

   #  Package the binaries into the build folder.
    package

The following files will be created:

  • $TOP_FOLDER/agilex5-ed-tsn-sgmii/src/sw/agilex5_mk_a5e065bb32aes1-gsrd-images/u-boot-agilex5-socdk-gsrd-atf/u-boot-spl-dtb.hex
  • $TOP_FOLDER/agilex5-ed-tsn-sgmii/src/sw/agilex5_mk_a5e065bb32aes1-gsrd-images/u-boot-agilex5-socdk-gsrd-atf/u-boot.itb
  • $TOP_FOLDER/agilex5-ed-tsn-sgmii/src/sw/agilex5_mk_a5e065bb32aes1-gsrd-images/sdimage.tar.gz

Programing

Note:

Programing Software Image

Write SD Card

  1. Extract the SD card image(sdimage.tar.gz) archive and obtain the file gsrd-console-image-agilex5.wic.

  2. Write the extracted SD card image (gsrd-console-image-agilex5_devkit.wic) to the micro-SD card using the included USB writer in the host computer:

On Linux, use the dd utility as shown below:

    # Determine the device associated with the SD card on the host computer. 
    cat /proc/partitions
    # This will return for example /dev/sdx
    # Use dd to write the image in the corresponding device
    sudo dd if=gsrd-console-image-agilex5.wic of=/dev/sdx bs=1M
    # Flush the changes to the SD card
    sync

On Windows, use the Win32DiskImager program. First, rename the gsrd-console-image-agilex5.wic to an .img file (sdcard.img, for example) and write the image as shown in the following figure:

Programing Hardware binary

Write QSPI Flash
  1. Download the JIC image, then write it to QSPI.
jtagconfig --setparam 1 JtagClock 16M
quartus_pgm -c 1 -m jtag -o "pvi;ghrd_a5ed065bb32ae6sr0.jic"

Linux Boot

  1. Open the serial port of Board A and Board B by using serial communication utility.

    Note: Follow the instructions in the Base GSRD configure-serial-console section, to configure and setup serial connection.

  2. Power cycle the board.

  3. Monitor the serial communication windows and wait for Linux to boot, use root as user name, and no password is required.

Running Ping Test

Use ifconfig to configure the IP address on both the Board DUT and start testing.

Example:-

ifconfig

eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
        inet 169.254.220.240  netmask 255.255.0.0  broadcast 169.254.255.255
        inet6 fe80::b068:1aff:fe7c:aa02  prefixlen 64  scopeid 0x20<link>
        ether b2:68:1a:7c:aa:02  txqueuelen 1000  (Ethernet)
        RX packets 347637  bytes 484781613 (462.3 MiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 178614  bytes 32669690 (31.1 MiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
        device interrupt 23  base 0x8000

eth1: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
        inet 169.254.225.122  netmask 255.255.0.0  broadcast 169.254.255.255
        inet6 fe80::e45c:b0ff:fee4:767c  prefixlen 64  scopeid 0x20<link>
        ether e6:5c:b0:e4:76:7c  txqueuelen 1000  (Ethernet)
        RX packets 328640  bytes 456017787 (434.8 MiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 171153  bytes 32075199 (30.5 MiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
        device interrupt 40

eth2: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
        inet 169.254.158.219  netmask 255.255.0.0  broadcast 169.254.255.255
        inet6 fe80::88be:c9ff:fe7a:7bec  prefixlen 64  scopeid 0x20<link>
        ether 8a:be:c9:7a:7b:ec  txqueuelen 1000  (Ethernet)
        RX packets 342615  bytes 477159176 (455.0 MiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 176198  bytes 32459349 (30.9 MiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
        device interrupt 57  base 0x8000

lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536
        inet 127.0.0.1  netmask 255.0.0.0
        inet6 ::1  prefixlen 128  scopeid 0x10<host>
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 2736892  bytes 166952698 (159.2 MiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 2736892  bytes 166952698 (159.2 MiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

# Execute this command on Board #A DUT: 
 ifconfig eth0 192.168.1.100
 ifconfig eth1 192.169.1.100
 ifconfig eth2 192.170.1.100 

# Execute this command on Board #B DUT: 
 ifconfig eth0 192.168.1.101
 ifconfig eth1 192.169.1.101
 ifconfig eth2 192.170.1.101

# Do ping to Board #B from Board #A

root@agilex5mka5e065bb32aes1:~# ping -I eth0 192.168.1.101
PING 192.168.1.101 (192.168.1.101): 56 data bytes
64 bytes from 192.168.1.101: seq=0 ttl=64 time=1.053 ms
64 bytes from 192.168.1.101: seq=1 ttl=64 time=0.330 ms
64 bytes from 192.168.1.101: seq=2 ttl=64 time=0.250 ms
64 bytes from 192.168.1.101: seq=3 ttl=64 time=0.178 ms
64 bytes from 192.168.1.101: seq=4 ttl=64 time=0.164 ms

--- 192.168.1.101 ping statistics ---
5 packets transmitted, 5 packets received, 0% packet loss
round-trip min/avg/max = 0.164/0.395/1.053 ms

root@agilex5mka5e065bb32aes1:~# ping -I eth1 192.169.1.101
PING 192.169.1.101 (192.169.1.101): 56 data bytes
64 bytes from 192.169.1.101: seq=0 ttl=64 time=0.587 ms
64 bytes from 192.169.1.101: seq=1 ttl=64 time=0.256 ms
64 bytes from 192.169.1.101: seq=2 ttl=64 time=0.194 ms
64 bytes from 192.169.1.101: seq=3 ttl=64 time=0.622 ms

--- 192.169.1.101 ping statistics ---
4 packets transmitted, 4 packets received, 0% packet loss
round-trip min/avg/max = 0.194/0.414/0.622 ms

root@agilex5mka5e065bb32aes1:~# ping -I eth2 192.170.1.101
PING 192.170.1.101 (192.170.1.101): 56 data bytes
64 bytes from 192.170.1.101: seq=0 ttl=64 time=0.906 ms
64 bytes from 192.170.1.101: seq=1 ttl=64 time=0.456 ms
64 bytes from 192.170.1.101: seq=2 ttl=64 time=0.280 ms
64 bytes from 192.170.1.101: seq=3 ttl=64 time=0.212 ms

--- 192.170.1.101 ping statistics ---
4 packets transmitted, 4 packets received, 0% packet loss
round-trip min/avg/max = 0.212/0.463/0.906 ms

Running iperf Test

  1. Execute below command on Board #A DUT.

    iperf3 --bind-dev eth0 -s -p 5201 > eth0.log & iperf3 --bind-dev eth1 -s -p 5202 > eth1.log & iperf3 --bind-dev eth2 -s -p 5203 > eth2.log &

  2. Execute below command on Board #B DUT. User need to configurate the inet address.

    iperf3 --bind-dev eth0 -c 169.254.220.240 -p 5201 & iperf3 --bind-dev eth1 -c 169.254.225.122 -p 5202 & iperf3 --bind-dev eth2 -c 169.254.158.219 -p 5203 &

  3. Output:

vi eth0.log

-----------------------------------------------------------
Server listening on 5201 (test #1)
-----------------------------------------------------------
Accepted connection from 169.254.247.159, port 54490
[  5] local 169.254.220.240 port 5201 connected to 169.254.247.159 port 54494
[ ID] Interval           Transfer     Bitrate
[  5]   0.00-1.00   sec  6.88 MBytes  57.6 Mbits/sec
[  5]   1.00-2.00   sec  8.12 MBytes  68.2 Mbits/sec
[  5]   2.00-3.00   sec  6.25 MBytes  52.4 Mbits/sec
[  5]   3.00-4.00   sec  7.38 MBytes  61.9 Mbits/sec
[  5]   4.00-5.00   sec  5.62 MBytes  47.2 Mbits/sec
[  5]   5.00-6.00   sec  7.00 MBytes  58.7 Mbits/sec
[  5]   6.00-7.00   sec  6.38 MBytes  53.5 Mbits/sec
[  5]   7.00-8.00   sec  6.38 MBytes  53.5 Mbits/sec
[  5]   8.00-9.00   sec  5.00 MBytes  41.9 Mbits/sec
[  5]   9.00-10.00  sec  7.50 MBytes  62.9 Mbits/sec
- - - - - - - - - - - - - - - - - - - - - - - - -
[ ID] Interval           Transfer     Bitrate
[  5]   0.00-10.01  sec  66.5 MBytes  55.7 Mbits/sec                  receiver

vi eth1.log

-----------------------------------------------------------
Server listening on 5202 (test #1)
-----------------------------------------------------------
Accepted connection from 169.254.164.238, port 34570
[  5] local 169.254.225.122 port 5202 connected to 169.254.164.238 port 34584
[ ID] Interval           Transfer     Bitrate
[  5]   0.00-1.00   sec  6.12 MBytes  51.3 Mbits/sec
[  5]   1.00-2.00   sec  6.38 MBytes  53.5 Mbits/sec
[  5]   2.00-3.00   sec  7.38 MBytes  61.9 Mbits/sec
[  5]   3.00-4.00   sec  6.62 MBytes  55.6 Mbits/sec
[  5]   4.00-5.00   sec  7.00 MBytes  58.7 Mbits/sec
[  5]   5.00-6.00   sec  7.00 MBytes  58.8 Mbits/sec
[  5]   6.00-7.00   sec  7.62 MBytes  63.9 Mbits/sec
[  5]   7.00-8.00   sec  7.25 MBytes  60.8 Mbits/sec
[  5]   8.00-9.00   sec  8.00 MBytes  67.1 Mbits/sec
[  5]   9.00-10.00  sec  6.50 MBytes  54.5 Mbits/sec
- - - - - - - - - - - - - - - - - - - - - - - - -
[ ID] Interval           Transfer     Bitrate
[  5]   0.00-10.01  sec  69.9 MBytes  58.6 Mbits/sec                  receiver

vi eth2.log

-----------------------------------------------------------
Server listening on 5203 (test #1)
-----------------------------------------------------------
Accepted connection from 169.254.16.245, port 50092
[  5] local 169.254.158.219 port 5203 connected to 169.254.16.245 port 50094
[ ID] Interval           Transfer     Bitrate
[  5]   0.00-1.00   sec  8.12 MBytes  68.1 Mbits/sec
[  5]   1.00-2.00   sec  6.38 MBytes  53.5 Mbits/sec
[  5]   2.00-3.00   sec  6.12 MBytes  51.4 Mbits/sec
[  5]   3.00-4.00   sec  6.25 MBytes  52.4 Mbits/sec
[  5]   4.00-5.00   sec  7.12 MBytes  59.8 Mbits/sec
[  5]   5.00-6.00   sec  6.50 MBytes  54.6 Mbits/sec
[  5]   6.00-7.00   sec  5.25 MBytes  44.0 Mbits/sec
[  5]   7.00-8.00   sec  6.75 MBytes  56.6 Mbits/sec
[  5]   8.00-9.00   sec  6.62 MBytes  55.6 Mbits/sec
[  5]   9.00-10.00  sec  7.25 MBytes  60.8 Mbits/sec
- - - - - - - - - - - - - - - - - - - - - - - - -
[ ID] Interval           Transfer     Bitrate
[  5]   0.00-10.00  sec  66.4 MBytes  55.7 Mbits/sec                  receiver

_Note : Update the Board #A DUT IP address using the above command._

SM TSN Config-3 Kernel Bootup

Note: For TSN and PTP tests, programming of the egress and ingress delays with delays of mrphy IP is required. Once you boot till kernel prompt, at the /home/root/ you will find the below files

  1. README_ tsn-delay-config
  2. tsn-delay-config

For the concurrent design, as the delay values needs to be updated for all the three interface eth0, eth1 and eth2, you just need to run the tsn-delay-config application just once at every power cycle (./tsn-delay-config), the application itself will detect automatically all the eth interfaces connected to the mrphy and will update the egress and ingress values. You can then run the PTP and TSN test cases.

Last update: October 20, 2025
Created: October 20, 2025
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