Baremetal Drivers

Overview

This page presents the pre-release of the Agilex 5 baremetal drivers. The purpose of the drivers is to provide developers with access to the low-level functionality of the HPS IP blocks, including the ability to access IP registers. The drivers are provided through the following git repository: https://github.com/altera-fpga/baremetal-drivers and are released under the MIT License.

Resources:

• Documentation
• API Construction
• Build Details
• Release Notes

Validation for this pre-release was done on the Intel Simics Simulator for Intel FPGAs and on Agilex 5 Premium Development Kit.

Demo

The following demo is provided:

• Agilex™ 5 E-Series Premium Development Kit Baremetal Hello World

Driver List

Name	Device	Documentation	Source
Clock Manager	Agilex 5	clkmgr	clkmgr
Combophy for SDMMC	Agilex 5	combophy	combophy
DMA	Agilex 5	dma	dma
ECC	Agilex 5	ecc	ecc
GIC	Agilex 5	gic	gic
General Purpose IO	Agilex 5	gpio	gpio
HPS Mailbox to SDM	Agilex 5	hps_mailbox	hps_mailbox
I2C	Agilex 5	i2c	i2c
I3C	Agilex 5	i3c	i3c
MMU	Agilex 5	mmu	mmu
NoC Firewall	Agilex 5	noc_firewall	noc_firewall
NoC Probe	Agilex 5	noc_probe	noc_probe
QSPI	Agilex 5	qspi	qspi
Reset Manager	Agilex 5	rstmgr	rstmgr
SDMMC	Agilex 5	sdmmc	sdmmc
SMMU	Agilex 5	smmu	sdmmc
SPI	Agilex 5	spi	spi
System Manager	Agilex 5	sysmgr	sysmgr
Timers	Agilex 5	timer	timer
UART	Agilex 5	uart	uart
Watchdog Timers	Agilex 5	watchdog	watchdog
XGMAC	Agilex 5	xgmac	watchdog

---

Last update: September 8, 2025
Created: May 25, 2024