4Kp60 Multi-Sensor HDR Camera Solution System Example Design for Agilex™ 5 Devices - Features

• Inputs:
  • Two MIPI D-PHY interfaces connected to two Framos FSM:GO IMX678 color camera modules with Sony Starvis2 8MP IMX678 sensor and Framos PixelMate MIPI CSI-2 interface.
  • Internal frontend Test Pattern Generator (TPG) supporting color bars and solid colors.

• Input selection switch

• Frontend video pipeline (CFA image):
  • Clipper IP.
  • ISP IP: Black Level Statistics (BLS), Defective Pixel Correction (DPC), Adaptive Noise Reduction (ANR), Black Level Correction (BLC), Vignette Correction (VC), White Balance Statistics (WBS), White Balance Correction (WBC), and Demosaic (DMS).

• Backend video pipeline (RGB image):
  • Histogram Statistics (HS) IP.
  • HDR Processing Pipeline:
    • 1D LUT IP - for operations such as Linear -> sRGB.
    • 3D LUT IP – for operations such as sRGB -> HLG.
    • Second 3D LUT IP – for operations such as HLG -> BT709.
  • Tone Mapping Operator (TMO) IP.
  • Un-Sharp Mask (USM) IP.
  • Warp IP.
  • Mixer IP:
    • TPG for uniform background (also supports color bars).
    • ISP Output overlay.
    • Logo overlay.
  • 1D LUT IP – for OETF operations such as Gamma, HLG, and PQ.

• Up to 4Kp60 10-bit Multi-rate DisplayPort output:
  • Selects best resolution and color depth supported by the connected Monitor. Supported modes:
    • 720p60, 1080p60, 4Kp30, 8-bit and 10-bit color depth.
    • 4Kp60 8-bit color depth.

• Video frame capture (3 color plane 16-bit color depth, 48-bit lossless TIFF image):
  • Sensor Raw Output (Grayscale RGB).
  • ISP Output (RGB).

Grayscale RGB

The single color plane of the sensor CFA image is copied into all 3 color planes on a per-pixel basis to produce an RGB image.

• Software stack running on HPS (quad-core ARM Cortex CPU):
  • Based on Poky Linux with additional Yocto layers supporting Altera® FPGAs.
  • Uses the Yocto build system.

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Last update: December 10, 2025
Created: October 6, 2025