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4Kp60 Multi-Sensor HDR Camera Solution System Example Design for Agilex™ 5 Devices - Software Functional Description

Overview

The primary software components are summarized in the following diagram and described below:

top-swm.

Software Top Block Diagram


Summary:

  • A Software application running on an embedded Linux system.
  • The application provides Web based UI to control the video pipeline and individual ISP IP.
  • User accesses Web UI from a remote PC or tablet over the network with a Web browser e.g. Chrome.
  • Linux system includes necessary drivers allowing the software application to access and control FPGA using register read/write interface.

Custom Linux distribution based on KAS

For the 4Kp60 Multi-Sensor HDR Camera Solution System Example Design for Agilex™ 5 Devices, Altera® provides the files to build the Linux system to run the ISP demo application. A custom version of Linux is built based on KAS (setup tool for Yocto projects, see KAS) and is composed of the following meta-layers:

KAS Reference

agilex-ed-camera/sw

Necessary elements in the meta-layers to bind Software and Hardware

This section details the various elements included in the meta-layers that facilitate running the camera application. These elements assist in "binding" the FPGA Soft IP with the Linus software running on the HPS. The following sections explain these elements to clarify the interaction between the HPS software stack and the FPGA soft IP. This interaction between the HPS and Camera IP serves as an example of how to interface any soft IP in the FPGA fabric with higher-level software.

Device Tree

Adds a custom .dtsi (device tree fragment) file to the main device tree for Linux kernel boot up stage socfpga_agilex5_socdk.dts. it compiles into a DTB (device tree blob) during kernel compilation and is added to the microSD card image during the Yocto build with the recipe device-tree.bb. The specific file for this design example (agilex5_vvp-isp-demo.dtsi), is appended using device-tree.bbappend directive. Look for these files in the different meta-layers provided.

FPGA Bitstream

Adds the agilex5_modkit_vvpisp.hps_first.core.rbf file to the build. The file is generated after Quartus® compilation. The *core.rbf file is added to the boot partition of the microSD card (renamed as top.core.rbf). The HPS configures the FPGA at initialization using u-boot load command in uboot.txt generated into boot.scr.uimg in the boot partition by u-boot-socfpga_%.bbappend (look for the files in the meta-layer). 

Found U-Boot script /boot.scr.uimg
1711 bytes read in 12 ms (138.7 KiB/s)
## Executing script at 81000000
crc32+ 12038144 bytes read in 627 ms (18.3 MiB/s)
............FPGA reconfiguration OK!
47645184 bytes read in 2435 ms (18.7 MiB/s)
42988 bytes read in 17 ms (2.4 MiB/s)
## Flattened Device Tree blob at 86000000
   Booting using the fdt blob at 0x86000000
Working FDT set to 86000000
   Loading Device Tree to 00000000feae5000, end 00000000feaf27eb ... OK
Working FDT set to feae5000

Starting kernel ...

FPGA configuration during HPS booting process


Look for the print "..... FPGA reconfiguration OK " during the device booting process, as shown in the previous figure to ensure the FPGA bitstream (top.core.rbf) has been properly loaded.

Additional u-boot configuration

Append to the u-boot arguments using IMAGE_BOOT_ARGS and IMAGE_BOOT_ARGS:append:agilex5_modular in different KAS/YOCTO configuration files to enable UIO drivers defined by uio_pdrv_genirq.of_id=generic-uio.

Using a Static IP Address

Linux on the microSD card obtains an IP address automatically via DHCP if the Ethernet network has a DHCP server. Alternatively, you may configure the network with a static IP address by editing the following file via the terminal interface: 

/etc/systemd/network/11-eth.network

Find the following lines in the file: 

[Network]
DHCP=yes

Replace the lines with the following content: 

[Network]
DHCP=no
Gateway=192.168.1.1
Address=192.168.1.123/24

Use the gateway and the static IP address as appropriate for your network. Save the file and reboot the board.


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Last update: September 11, 2025
Created: September 11, 2025
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