Holoscan Sensor Bridge MIPI to 10GbE System Example Design for Agilex™ 5 Devices¶

The design is compatible with Altera® Quartus® Prime Pro Edition version 25.1 Linux.

Overview¶

The Holoscan Sensor Bridge MIPI to 10GbE System Example Design for Agilex™ 5 Devices demonstrates an implementation of using industry-standard Mobile Industry Processor Interface (MIPI) D-PHY and MIPI CS1-2 interface on Agilex™ 5 FPGAs to integrate to a Holoscan processing flow.

The MIPI interface supports up to 2.5Gbps per lane and up to 8x lanes per MIPI interface, enabling seamless data reception from multiple 4K image sensors to the FPGA fabric for further processing. Each MIPI CSI-2 IP instance converts pixel data to AXI4-Streaming outputs, enabling connectivity to other IP cores within Altera's Video and Vision Processing (VVP) Suite.

The FPGA design comprises a MIPI D-PHY and MIPI CSI-2 interface connected to an NVIDIA Holoscan Sensor Bridge IP and Altera's Low Latency Ethernet 10G IP.

The software comprises a number of demonstration applications running within NVIDIA Holoscan Sensor Bridge SDK.

High-Level Block Diagram of the Holoscan Sensor Bridge System Example Design

Pre-requisites¶

Follow the instructions provided in the section to run the Holoscan Sensor Bridge MIPI to 10GbE System Example Design for Agilex™ 5 Devices.

Hardware Requirements¶

Agilex™ 5 FPGA E-Series 065B Modular Development Kit.

Agilex™ 5 FPGA E-Series 065B Modular Development Kit

1 or 2 Framos FSM:GO IMX678C Camera Modules, with:
- Wide 110deg HFOV Lens, or
- Medium 100deg HFOV Lens, or
- Narrow 54deg HFOV Lens.
Mount/Tripod
- Framos Tripod Mount Adapter.
- Tripod.
A Framos cable for PixelMate MIPI-CSI-2 for each Camera Module:
- 150mm flex-cable, or
- 300mm micro-coax cable.
USB Micro B JTAG Cable (for JTAG programming).
10GBase-T SFP+ to RJ45 module
Cat6 Ethernet Cable
NVIDIA Jetson Orin AGX Devkit

Software Requirements¶

NVIDIA host system running Holoscan SDK
- Set up the host system following : NVIDIA Host Setup
Note

When cloning the Holoscan Sensor Bridge Repo use the Altera mirror:
```
git clone -b altera-2.3.0 --single-branch https://github.com/altera-fpga/holoscan-sensor-bridge
```

Download the pre-built FPGA¶

Download the Agilex™ 5e Modular Development board SOF binaries:

Binaries

Source	Link	Description
SOF	AGX_5E_065B_Modular_DevKit_HSB_MIPI_1_10GbE.sof	Programs the board to connect to the Holoscan system

Getting Started - run with pre-built FPGA¶

Follow the instructions provided in this section to run the Holoscan Sensor Bridge MIPI to 10GbE System Example Design for Agilex™ 5 Devices.

Setting Up your Modular Development Board¶

Warning

Handle ESD-sensitive equipment (boards, microSD Cards, Camera sensors, etc.) only when properly grounded and at an ESD-safe workstation

Configure the board switches as shown:

Modular Development Board - Default Switch Positions

Connect micro USB cable between the carrier board (J35) and the Host PC. This will be used for JTAG communication. Look at what ports are enumerated on your Host computer. There should be a series of four.

Board Connections

Board and NVIDIA Host System Setup¶

Warning

Handle ESD-sensitive equipment (boards, microSD Cards, Camera sensors, etc.) only when properly grounded and at an ESD-safe workstation

Make the required connections between the NVIDIA Host System and the Modular Development board as shown in the following diagram:

Development Kit and Host System Connection diagram

Connect the Framos cable(s) between the Framos Camera Module(s) and the Modular Development board taking care to align the cable(s) correctly with the connectors (pin 1 to pin 1). The current design only supports a single camera which should be connected to MIPI 0.

Board MIPI connections

Board MIPI and Ribbon Cable

Camera and Ribbon Cable

Running the Demonstrations¶

Program the FPGA SOF¶

To program the FPGA using SOF:
- Power down the board. Set MSEL=JTAG by setting the S4 dip switch on the SOM to OFF-OFF.
  - This prevents the starting of any bootloader and FPGA configuration after power up and until the SOF is programmed over JTAG.
- Power up the board.
- Either use your own or download the pre-built SOF image, and program the FPGA with either the command:
```
quartus_pgm -c 1 -m jtag -o "p;AGX_5E_065B_Modular_DevKit_HSB_MIPI_1_10GbE.sof"
```
- or, optionally use the Quartus® Programmer GUI:
  - Launch the Quartus® Programmer and Configure the "Hardware Setup..." settings as follows:

Programmer GUI Hardware Settings

Click "Auto Detect", select the device A5EC065BB32AR0 and press "Change File.."

Programmer after "Auto Detect"

Select your AGX_5E_065B_Modular_DevKit_HSB_MIPI_1_10GbE.sof file. Check the "Program/Configure" box and press the "Start" button (see below). Wait until the programming has been completed.

Programming the FPGA with SOF file

Demonstrations¶

The following examples applications are available to demonstrate the Holoscan Sensor Bridge MIPI to 10GbE System Example Design for Agilex™ 5 Devices.

Set up host system¶

Set up the NVIDIA host system as per instructions.

Build the Demo Docker Container¶

Build the holoscan sensor bridge demonstration container. For systems with dGPU or DGX Spark,

cd <holoscan sensor bridge>
sh docker/build.sh --dgpu

For systems with iGPU,

cd <holoscan sensor bridge>
sh docker/build.sh --igpu

To run a demo application, start the demo container¶

cd <holoscan sensor bridge>
sh docker/demo.sh

From within the Demo container run one of the following demos:¶

* Simple Playback Example

python examples/linux_agx5_player.py

* YOLOv8 Body Pose Example

Follow instructions to download YOLOv8 ONNX Model

python examples/linux_body_pose_estimation_agx5.py

TAO PeopleNet Example

Follow instructions to download tao peoplenet model

python examples/linux_tao_peoplenet_agx5.py

Recommended User Flows¶

Sources¶

The sources listed in this table are the most current and highly recommended for Quartus® 25.1 builds. Users are advised to utilize the updated versions of these building blocks in production environments. Please note that this is a demonstration design and is not suitable for production or final deployment.

System Example Design Source Repository

Component	Location	Branch
Assets Release Tag	https://github.com/altera-fpga/agilex-ed-hsb-mipi/releases/tag/rel-25.1-2507-4	main
Repository	https://github.com/altera-fpga/agilex-ed-hsb-mipi	main
Holoscan SDK	https://github.com/altera-fpga/holoscan-sensor-bridge	altera-2.3.0

With the available resources, you can create and modify, build and compile, and execute the Holoscan Sensor Bridge MIPI to 10GbE System Example Design for Agilex™ 5 Devices. There are 2 recommended flows that you can explore:

User Flow 1: Getting Started - Running with pre-built FPGA.
User Flow 2: Use the Modular Design Toolkit (MDT) Flow to build FPGA SOF

Flows¶

Recommended User Flows

User Flow	Description	User Flow 1	User Flow 2
Pre-requisites	Hardware Requirements.	✓	✓
	Software Requirements to run.	✓	✓
	Download the Pre-built FPGA.	✓	✗
HW-Compilation	Creating and Building the Design based on the Modular Design Toolkit (MDT) Flow	✗	✓
Programming	Setting Up your Modular Development Board.	✓	✓
	Program the FPGA SOF.	✓	✓
Running	Board and Host System Setup.	✓	✓
	Running Demonstrations.	✓	✓

Other Repositories Used¶

Component	Location	Branch
Modular Design Toolkit	https://github.com/altera-fpga/modular-design-toolkit	rel-25.1

Useful User Manuals and Reference Materials¶

Agilex™ 5 FPGA E-Series 065B Modular Development Kit.

Notices & Disclaimers¶

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Last update: December 10, 2025
Created: December 10, 2025