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General Purpose I/O Driver for Hard Processor System

Last updated: January 05, 2026

Upstream Status: Upstreamed

Devices supported: Agilex3, Agilex 5, Agilex 7

Introduction

The Hard Processor System (HPS) provides two General-Purpose I/O (GPIO) interface modules.

The GPIO interface supports Digital debounce, configurable interrupt mode, and has up to 48 dedicated I/O pins. For more information please refer to the Agilex 5 Hard Processor System Technical Reference Manual.

The figure below shows a block diagram of the GPIO interface:

a5_gpio_block_diagram

Driver Sources

The source code for this driver can be found at https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpio/gpio-dwapb.c.

Driver Capabilities

  • GPIO muxed between I2C and SPI.
  • Interrupt propagation between the device and logic on board.
  • Control other circuitry on board.
  • Digital debounce.
  • Configurable interrupt mode.

Kernel Configurations

CONFIG_GPIO_DWAPB

gpio_kconfig

Device Tree

Example Device tree location:

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi

gpio_device_tree

Test Procedure

In the following sub-sections are described some common GPIO operations that are performed through the GPIO driver. These are exercised from the Linux shell once the GPIO driver has been probed. The test procedures are exercised using the /sys/class/gpio interface.

This test procedure was exercised on Agilex 5 E-Series Premium Development Kit using the GSRD for HPS Enablement Board (booting from SD Card) from 24.3.1 release which uses Linux Kernel 6.6.51.

When the driver has been initialized you will se the following under this GPIO interface:

  ls /sys/class/gpio/
export  gpiochip512  gpiochip536  gpiochip560  gpiochip592  gpiochip624  unexport

NOTE: You can determine which GPIOs are available using the information provided by the gpiochipXYZ directories included in the /sys/class/interface interface. Each one of the gpiochipXYZ represents a GPIO controller. In the following example you can see that the GPIO controller referred as gpiochip512 starts in the GPIO 512 and is extended to 24 pins going from 512 to 535 using the information provided by base and ngpio. You can also see which is the base address of this GPIO controller in the memory map using the information in label.

ls /sys/class/gpio/gpiochip512/          
base       device/    label      ngpio      power/     subsystem/ uevent
cat /sys/class/gpio/gpiochip512/base
512
cat /sys/class/gpio/gpiochip512/ngpio 
24  
cat /sys/class/gpio/gpiochip512/label 
10c03200.gpio

Step 1: Export a GPIO Pin

  1. Export a GPIO Pin: You export a pin to make it available to the user for control through the /sys/class/gpio/ interface. Use the echo command to export a GPIO pin. For example, to export GPIO pin 512:

    echo 512 > /sys/class/gpio/export
ls /sys/class/gpio
export    gpio512  gpiochip512  gpiochip536  gpiochip560  gpiochip592  gpiochip624  unexport
ls /sys/class/gpio/gpio512
active_low  device  direction  edge  power  subsystem  uevent  value
    Observe that once the pin has been export, a new interface named gpio512 is created. This provides additional interfaced under this that will help to configure, control and get information from this pin.

  2. Set Direction: Set the direction of the GPIO pin to either input or output. To set it as an output:

    echo out > /sys/class/gpio/gpio512/direction

Step 2: Toggle GPIO Pin Value

  1. Write a Value: Write a value (either 0 or 1) to the GPIO pin. Set a value of 1:

    echo 1 > /sys/class/gpio/gpio512/value

  2. Read the Value: Read back the current value of the GPIO pin.

    cat /sys/class/gpio/gpio512/value

  3. Toggle the value: Change the value to the opposite and verify it.

    echo 0 > /sys/class/gpio/gpio512/value
cat /sys/class/gpio/gpio512/value

Step 3: Unexport the GPIO Pin

  1. Unexport the GPIO Pin: After you are done, unexport the GPIO pin to free up resources.

    echo 512 > /sys/class/gpio/unexport

Known Issues

None known

Notices & Disclaimers

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Last update: December 10, 2025
Created: May 25, 2024
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