QSPI Driver for Hard Processor System (HPS)¶
Last updated: May 07, 2025
Upstream Status: Not Upstreamed
Devices supported: Agilex 5
Introduction¶
The Quad Serial Peripheral Interface (QSPI) driver manages the QSPI controller in the HPS. The QSPI has the capability to access serial NOR Flash connected to the Secure Device Manager (SDM) QSPI. The QSPI controller supports standard SPI Flash devices as well as high-performance dual and quad SPI Flash devices. The QSPI controller module features are:
- SPIx1, SPIx2, or SPIx4 (QSPI) serial NOR flash devices
- Supported clock frequencies up to 166 MHz
- Direct access and indirect access modes
- Single I/O, dual I/O, or quad I/O instructions
- Up to four chip selects
- Configurable clock polarity and phase
- Programmable write-protected regions
- Programmable delays between transactions
To find out more about the QSPI controller within the HPS please refer to the Intel Agilex 5 Hard Processor System Technical Reference Manual.
Driver Capabilities¶
- Initialize and configuration of the QSPI controller.
- Handles data transfer and address.
Driver Sources¶
The source code for this driver can be found at https://github.com/altera-opensource/linux-socfpga/blob/socfpga-6.1.55-lts/drivers/spi/spi-cadence-quadspi.c.
Kernel Configurations¶
CONFIG_SPI_CADENCE_QUADSPI
Device Tree¶
Example Device tree location:
Known Issues¶
None kKnown
Notices & Disclaimers¶
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Created: May 25, 2024