System Memory Management Unit (SMMU) Driver for Hard Processor System¶
Last updated: April 22, 2025
Upstream Status: Upstreamed
Devices supported: Agilex 5
Introduction¶
SMMU converts virtual addresses to physical addresses for external peripheral devices. This allows multiple external devices to perform direct memory access (DMA) to the entire range of the system physical memory.
As an example, certain peripheral devices limited to accessing only 24 bits of address space would now be able to access all 64 bits addresssing through the memory translation tables of the SMMU.
The SDM SMMU is used solely by the FCS Cryptography feature. The accelerator like FCS_Crytpo sends a VA to SMMU and SMMU queries the PA from the page table.
SMMU registers are configured through ARM Trusted firmware (ATF) BL31 SMC calls by the Crytography device drivers. The ATF performs default SMMU initializations of the stream IDs through the system manager and SMMU secure registers configuration during the boot-up process.
For More information please refer to the following link:
Agilex 5 Hard Processor System Technical Reference Manual
Driver Sources¶
The source code for this driver can be found at:
Driver Capabilities¶
- Queue manipulation, sizing
- Command queue locking or insertion
- Error reporting
- Updating Stream Table Entry
Kernel Configurations¶
CONFIG_ARM_SMMU_V3
Device Tree¶
Example Device tree location to configure the smmu:
Known Issues¶
None known
Notices & Disclaimers¶
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Created: May 25, 2024