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4Kp60 Multi-Sensor Camera Stitch Solution System Example Design for Agilex™ 5 Devices

The design is compatible with Altera® Quartus® Prime Pro Edition version 26.1 Linux.

Overview

The 4Kp60 Multi-Sensor Camera Stitch Solution System Example Design for Agilex™ 5 Devices demonstrates a practical glass-to-glass camera stitch solution. The exclusive support for industry-standard Mobile Industry Processor Interface (MIPI) D-PHY and MIPI CSI-2 interface on Agilex™ 5 FPGAs provides a powerful tool for camera product development.

An example of Image Stitching
stitch-overview

The MIPI interface supports up to 2.5Gbps per lane and up to 8x lanes per MIPI interface, enabling seamless data reception from multiple 4K image sensors to the FPGA fabric for further processing. Each MIPI CSI-2 IP instance converts pixel data to AXI4-Streaming outputs, enabling connectivity to other IP cores within Altera®'s Video and Vision Processing (VVP) Suite.

The design is a hardware-software co-design, whose hardware component comprises dual Image Signal Processors (ISPs) with Stitch, various VVP IPs, Hard Processor Subsystem (HPS) and various connectivity IPs. The software stack is Linux based and runs on the HPS.

The hardware includes a multi-sensor input video switch feeding into dual Image Signal Processing (ISP) subsystems. Each ISP is a video processing pipeline incorporating many VVP IP cores including a high performance Warp IP core for geometric distortion correction and downscaling to 2Kp60. Each ISP processes the raw sensor image data into RGB video data which feed into the Stitch video processing pipeline to blend the images together, side by side to form a wide 4K x 1k output image. In addition, the pipeline also includes a 3D-LUT IP for color transformations and conversions and the adaptive local tone mapping (TMO) for handling wide dynamic range scenes. The design creates a full 4Kp60 output letterbox style image from the stitched output image. The design drives the resulting 4Kp60 streaming video output data through an Altera® DisplayPort IP.

The software stack consists of an application software binary running on Linux operating system with various layers of drivers. The backend part of the application software interrogates the hardware, discovers the IP components dynamically and configures them. Multiple feedback loops monitor the hardware and keep various hardware components in lockstep. Some of the notable feedback loops are Automatic White Balance (AWB), Auto Exposure (AE), and Adaptive Noise Reduction (ANR) algorithms, reading their relevant statistics and adjusting various coefficients and Look Up Tables (LUTs) in real time. The frontend of the software creates a web based Graphical User Interface (GUI) and runs it over a web server.

Detailed Design

The detailed design can be found at camera_4k_stitch.md

The project GitHub repository can be found at https://github.com/altera-fpga/agilex5-ed-camera


Notices & Disclaimers

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Last update: August 14, 2026
Created: August 14, 2026
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