4Kp30 Camera Lite Solution System Example Design for Agilex® 3 Devices¶
Overview¶
The 4Kp30 Camera Lite Example Design for Agilex® Devices demonstrates a practical, area-efficient, and cost-efficient glass-to-glass camera system solution. Support for the industry-standard Mobile Industry Processor Interface (MIPI) D-PHY and MIPI CSI-2 interfaces on Agilex® FPGAs provides a powerful platform for camera product development.
The MIPI interface supports up to 2.5 Gbps per lane and up to eight lanes per MIPI interface, enabling seamless data reception from a 4K image sensor into the FPGA fabric for further processing. The MIPI CSI-2 IP converts pixel data to AXI4-Stream outputs, which enables connectivity to other IP cores in the Altera® Video and Vision Processing (VVP) Suite.
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The design is a hardware and software co-design:
- The hardware path includes a sensor feeding an Image Signal Processing (ISP) subsystem. The ISP subsystem is a video processing pipeline that incorporates VVP IP cores to convert raw sensor image data into RGB video data. The design drives the resulting 4Kp30 streaming video output through an Altera® DisplayPort IP.
The following diagram provides an overview of the interaction between the software running on the Nios® V processor and the hardware components in the programmable logic.
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- The software stack is a bare-metal application that runs on an embedded Nios® V soft processor. The backend of the software application interrogates the hardware, discovers the IP components dynamically, and configures them. Multiple feedback loops monitor the hardware and keep components in lockstep—for example, DisplayPort Hot Plug Detect (HPD). The frontend of the software creates a terminal-based user interface and runs it over a JTAG UART.
The following figure shows the main hardware components and subsystems.
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Detailed Design¶
The detailed design can be found at User Guide
The project GitHub repository can be found at https://github.com/altera-fpga/agilex3-ed-camera/tree/rel/26.1.1
Notices & Disclaimers¶
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