4Kp60 Multi-Video Connectivity Solution System Example Design for Agilex™ 5 Devices¶
Overview¶
The 4Kp60 Multi-Video Connectivity System Example Design for Agilex™ 5 Devices shows how a single FPGA device can unify HDMI, DisplayPort (DP), and serial digital interface (SDI) video using a common streaming protocol. The design converts between video protocols and processes video between these interfaces in real time.
The design receives SDI video through an FPGA mezzanine card (FMC) daughter card, and receives HDMI and DP video through the onboard connectors on the modular development kit. All three video interfaces support standards up to UHD and can deliver video resolutions up to 4Kp60 to the FPGA fabric. Each interface converts pixel data to AXI4-Stream, which provides connectivity to other IP cores in the Altera Video and Vision Processing (VVP) Suite.
The design comprises the following hardware and software components:
- Software—A bare-metal application that runs on a Nios® V soft processor. The application provides runtime control and debug menus through a JTAG UART interface.
The following figure shows the interaction between the Nios® V software and the hardware in the FPGA fabric.
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- Hardware—Three video datapaths, one for each input and output video interface. Each datapath includes a frame buffer and a video scaler that decouple frame rates and active video resolutions between the input and output interfaces. Input and output video switches route input video to the output interfaces that you select in the software application. The design also includes an input test pattern generator (TPG), additional VVP Suite IP cores for video preprocessing, and an embedded processor subsystem.
The following figure shows the main hardware components and subsystems.
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Detailed Design¶
The detailed design can be found at doc-mvc.md
The project GitHub repository can be found at https://github.com/altera-fpga/agilex5e-ed-mvc-video
Notices & Disclaimers¶
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Created: September 18, 2026