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4Kp60 SDI-based Genlock HDR Video Pipeline Solution System Example Design for Agilex™ 5 Devices

Overview

The 4Kp60 SDI-based Genlock HDR Video Pipeline System Example Design for Agilex™ 5 Devices demonstrates three-dimensional lookup table (3D LUT)-based conversion between high dynamic range (HDR) and standard dynamic range (SDR) video. HDR-to-SDR conversion is required for interoperability between legacy and emerging formats in broadcast workflows.

The following figure shows example SDI input and output images, after applying a 3D LUT on the input image.

SDI Input Image
SDI Output Image
Input Capture Output Capture

The design receives video through an industry-standard serial digital interface (SDI) on an FPGA mezzanine card (FMC) daughter card. The SDI interface supports video standards up to 12G-SDI and can deliver video resolutions up to 4Kp60 to the FPGA fabric. The SDI IP converts pixel data to AXI4-Stream, which provides connectivity to other IP cores in the Altera Video and Vision Processing (VVP) Suite.

The design comprises hardware and software components:

  • The software is a bare-metal application that runs on a Nios® V soft processor. The application provides runtime control and debug menus through a JTAG UART interface.

The following figure shows the interaction between the Nios® V software and the hardware in the FPGA fabric.

SDI-based Genlock HDR Video Pipeline Example Design—Top-Level System Block Diagram
Input Capture2

  • The hardware includes one bypass path and two HDR datapaths. Each path is fully genlocked and does not use a frame buffer. The hardware also includes VVP Suite IP cores and an embedded processor subsystem. Each HDR datapath contains a 3D LUT IP core that is initialized with 3D cube files that implement a specific HDR-to-SDR conversion.

    A Mixer IP at the output of the pipeline combines the HDR and bypass streams with a background layer from the Test Pattern Generator (TPG) IP into a single video frame. The software can configure the Mixer IP for side-by-side display of the input video and the 3D LUT result. Processed video leaves the design through the SDI transmit interface.

    The following figure shows the main hardware components and subsystems.

SDI-based Genlock HDR Video Pipeline Example Design—Top-Level Hardware Block Diagram
Input Capture3

Detailed Design

The detailed design can be found at doc-genlock-hdr.md

The project GitHub repository can be found at https://github.com/altera-fpga/agilex5-ed-genlock-hdr-video


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Last update: September 18, 2026
Created: September 18, 2026
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