HPS TSN RGMII System Example Design User Guide

Introduction¶

IEEE Ethernet is a core technology which is a backbone for IT operations and was designed to provide best effort communication suitable for IT operations. Operational Technology vendors have innovatively used Core IEEE Ethernet technology with proprietary solutions for enabling time-bounded communication. To address the need for precision timing, traffic shaping, and time-bounded communication over networks, IEEE introduced a suite of standards known as Time Sensitive Networking (TSN).

Agilex™ 5 E-Series is designed as an end point for Industrial automation application with support for the following TSN protocols:

Time Synchronization Protocols:
- IEEE 1588-2008 Advanced Timestamp (Precision Time Protocol - PTP):
  - Function: Provides sub-microsecond accuracy for time synchronization between computing systems over a local area network.
  - Key Features: 2-step synchronization, PTP offload, and timestamping.
  - Use Case: Synchronizing industrial devices to operate in unison, ensuring coordinated actions across factory or plant operations.
- IEEE 802.1AS (Timing and Synchronization):
  - Function: A profile of PTP (version 2) that ensures precise time synchronization in a hierarchical master-slave architecture.
  - Key Features: Prioritizes accuracy and variability of timing, crucial for industrial and automotive systems.
  - Use Case: Synchronizing devices to a common time for optimal operation and collaboration.

Credit Based Shaper Protocol:
- IEEE 802.1Qav (Time-Sensitive Streams Forwarding and Queuing):
  - Function: Provides low-latency, time-synchronized delivery of audio and video streams over Ethernet networks.
  - Key Features: Credit-based shaper ensuring end-to-end guaranteed bandwidth with fairness to best-effort traffic.
  - Use Case: Ensuring dedicated bandwidth for audio-video bridging (AVB) streams with minimal latency.

Traffic Scheduling Protocols:
- IEEE 802.1Qbv (Time-Scheduled Traffic Enhancements):
  - Function: Enables the transmission of frames at specific scheduled times within microsecond ranges.
  - Key Features: Critical for time-sensitive scheduled traffic in industrial applications.
  - Use Case: Facilitating precise, time-critical communication for industrial devices like PLCs and drives.
- IEEE 802.1Qbu (Frame Preemption):
  - Function: Allows high-priority frames to preempt lower-priority frames, reducing latency and jitter.
  - Key Features: Utilizes Express Media Access Control (eMAC) and Preemptable Media Access Control (pMAC).
  - Use Case: Ensuring high-priority frames arrive with fixed latency, crucial for applications requiring consistent timing.

These TSN standards collectively enable precise timing, traffic shaping, and time-bounded communication, making them indispensable for applications requiring high reliability and determinism.

The details of TSN is not in the scope of this document. Here are some reference to the TSN specifications

TSN HPS RGMII System Example Design Overview¶

The Time Sensitive Network (TSN) through Hard Processor System (HPS) IO System Example Design (SED) is a reference design running on the Agilex™ 5 E-Series 065B Modular Development Kit.
This System Example Design comprises the following components:

Hardware Reference Design (GHRD)
Reference HPS software including:
- Arm Trusted Firmware
- U-Boot
- Linux Kernel
- Linux Drivers
- Sample Applications

TSN Solution Architecture for this SED is illustrated as:

[Note:] This is a pre-production release of Agilex™ 5 TSN HPS RGMII System Example Design, on Agilex™ 5 FPGA E-Series 065B Modular Development.

Prerequisites¶

This system example design is based on the Agilex 5 E-Series Modular Development Kit GSRD. It is recommended that you familiarize yourself with the GSRD development flow before proceeding with this design. The TSN through HPS IO System Example Design will be implemented on the HPS Enablement Expansion Board (also referred as HPS Daughter Card), which is included with the development kit.

Development Kit¶

This Example Design targets the Agilex 5 FPGA E-Series 065B Modular Development Kit, utilizing the HPS. Refer to GSRD#Development Kit for details about the board, including how to install the HPS Daughter Card.

Altera® Agilex™ 5 FPGA E-Series 065B Modular Development Kit
HPS Enablement Expansion Board. Included with the development kit.
Mini USB Cable
Micro USB Cable
Ethernet Cable
Micro SD card and USB card writer

Altera® Agilex™ 5 FPGA E-Series 065B Modular Development Kit:

Development Environment¶

Host PC with:

64 GB of RAM. Less will be fine for only exercising the binaries, and not rebuilding the GSRD.
Linux OS installed. Ubuntu 22.04LTS was used to create this page, other versions and distributions may work too.
Serial terminal (for example GtkTerm or Minicom on Linux and TeraTerm or PuTTY on Windows)
Altera® Quartus® Prime Pro Edition version. Used to recompile the hardware design. If only writing binaries is required, then the smaller Altera® Quartus® Prime Pro Edition Programmer is sufficient.
The prebuilt binaries were built using Altera® Quartus® 26.1
The instructions for rebuilding the binaries use Altera® Quartus® 26.1
Local Ethernet network, with DHCP server
Internet connection. For downloading the files, especially when rebuilding the GSRD.

Release Contents¶

This page documents content testing with prebuild binaries flow and testing with complete flow.

See [HPS GSRD User Guide for the Agilex™ 5 E-Series Modular Dev Kit] (https://altera-fpga.github.io/rel-26.1/embedded-designs/agilex-5/e-series/modular-065b/gsrd/ug-gsrd-agx5e-modular-065b/)
- See Prerequisites
- See Prebuild Binaries
- See Component Versions
- See Exercise-prebuilt-binaries

TSN RGMII Architecture¶

This system example design showcases Ethernet design through the HPS IO on the HPS Enablement Expansion Board, with support for TSN features including IEEE 802.1AS, IEEE 802.1Qav, IEEE 802.1Qbv, IEEE 802.1Qbu.

HPS Peripherals connected to HPS Enablement Expansion Board:
- Micro SD Card
- EMAC
- HPS JTAG debug
- UART

User Flow¶

There are two ways to test the design based on use case.

User Flow 1: Testing with Prebuilt Binaries

User Flow 2: Testing Complete Flow build GSRD 2.0

User Flow	Description	Required for Userflow#1	Required for Userflow#2
Environment Setup	Tools Download and Installation	Yes	Yes
	Install dependencies for SW compilation	No	Yes
Compilation	Simulation	No	No
	Hardware Compilation	No	Yes
	Software Compilation	No	Yes
Programming	Programming the binaries	Yes	Yes
	Linux boot	Yes	Yes
Testing	Run Test Application	Yes	Yes

Linux Boot¶

Power down board
Set MSEL dipswitch S4 on SOM to ASX4 (QSPI): ON-ON
Power up the board
Wait for Linux to boot, use root as user name, and no password will be requested.

Testing¶

For the purpose of demonstration, 2 development kits (refer to GSRD) will be required with Ethernet connected back to back from one board to another.

Note: Ethernet port is on the HPS Enablement Expansion Board attached.

Running Ping Test¶

Use ifconfig to configure the IP address on both the Devkit DUT and start testing.

Example:-

Devkit #1 : $ ifconfig eth0 192.168.1.100

Devkit #2 : $ ifconfig eth0 192.168.1.200

Running iperf Test:¶

Execute below command on Devkit #1 DUT.

iperf3 -s eth0
Execute below command on Devkit #2 DUT.

iperf3 eth0 -c 192.168.1.100 -b 0 -l 1500

Note : Update the Devkit #1 DUT IP address in above command.

Run TSN Application¶

The following examples are demonstrated using 2 units of the Agilex 5 platform. Please take note of the notation "[Board A or B]". The following steps assumes both platforms are connected to each other via an Ethernet connection.

1. Boot to Linux

2. Navigate to the tsn directory

cd tsn

Configuration for Both Boards

Step I: Setup Environment Path on Both Boards

3. Board A

export LIBXDP_OBJECT_PATH=/usr/lib64/bpf
export LD_LIBRARY_PATH=/usr/lib/custom_bpf/lib

4. Board B

export LIBXDP_OBJECT_PATH=/usr/lib64/bpf
export LD_LIBRARY_PATH=/usr/lib/custom_bpf/lib

TXRX-TSN App

Step II: Run Configuration Script

5. Board A: Run the configuration script and wait for it to configure the IP and MAC address, start clock synchronization, and set up TAPRIO qdisc.

./run.sh agilex5 eth0 vs1a setup

6. Board B: Run the configuration script and wait for it to configure the IP and MAC address, start clock synchronization, and set up ingress qdiscs.

./run.sh agilex5 eth0 vs1b setup

Step III: Start the Application

7. Board B: Run the application.

./run.sh agilex5 eth0 vs1b run

8. Board A: Immediately after starting the application on Board B, run the application on Board A.

./run.sh agilex5 eth0 vs1a run

Post-Test Procedure

Once the test is completed, copy the following files from Board B (listener) to the host machine:

afpkt-rxtstamps.txt
afxdp-rxtstamps.txt

Generating Latency Plot Using Excel

Import 'afpkt-rxtstamps.txt' and 'afxdp-rxtstamps.txt' to excel in 2 seperate sheets.

Plot Column 1 for each sheets using Scatter chart,

This will generate plot for AFPKT and AFXDP with latency(on Y-axis) against packet count (on X-axis).

The latency for this design example can be seen as below:

Run Time Synchronization commands¶

You may use the following command guide to perform time synchronization on the Agilex™ 5 system using PTP4L and PHC2SYS, and to obtain delay values

End-to-End PTP master and slave synchronization

Board B (as slave):

ptp4l -i eth0  -s -H -E -2 -m

-i  eth0: This option specifies the `eth0` as the network interface to use for PTP.
-s  This option enables the slave-only mode. 
-H  This option enables hardware time stamping. 
-E  This option selects the end-to-end (E2E) delay measurement mechanism. This is the default.The E2E mechanism is also referred to as the delay “request-response” mechanism.
-2  Use Ethernet Layer (L2)
-m  This option enables printing of messages to the standard output.

Boards A (as master):
```
ptp4l -i eth0  -H -E -2 -m
```

At Board B (as slave), perform sync on local System Clock with EMAC Hardwware Clock.
```
phc2sys -s eth0 -w -m -c CLOCK_REALTIME -O 0 -n 0
```

Peer-to-Peer PTP synchronization:

Board B (as slave):
```
slave: ptp4l -i eth0  -s -H -P -2 -m
```
-P: This option enables the use of the Peer Delay Mechanism.

Board A (as master):
```
master: ptp4l -i eth0  -H -P -2 -m
```

At Board B (as slave), perform sync on local System Clock with EMAC Hardwware Clock.
```
phc2sys -s eth0 -w -m -c CLOCK_REALTIME -O 0 -n 0
```

gPTP synchronization:

Board B (as slave):

ptp4l -i eth0  -s -H -P -2 -m --transportSpecific=1

Board A (as master):

ptp4l -i eth0  -H -P -2 -m --transportSpecific=1

At Board B (as slave), perform sync on local System Clock with EMAC Hardwware Clock.

phc2sys -s eth0 -w -m --transportSpecific 1 -c CLOCK_REALTIME -O 0 -n 0

Notices & Disclaimers¶

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Last update: May 6, 2026
Created: May 6, 2026