Holoscan Sensor Bridge MIPI to 25GbE System Example Design for Agilex™ 5 Devices¶
The design is compatible with Altera® Quartus® Prime Pro Edition version 26.1 Linux.
Overview¶
The Holoscan Sensor Bridge MIPI to 25GbE System Example Design for Agilex™ 5 Devices demonstrates an implementation of using industry-standard Mobile Industry Processor Interface (MIPI) D-PHY and MIPI CS1-2 interface on Agilex™ 5 FPGAs to integrate to a Holoscan processing flow.
The MIPI interface supports up to 3.5Gbps per lane and up to 8x lanes per MIPI interface, enabling seamless data reception from multiple 4K image sensors to the FPGA fabric for further processing. Each MIPI CSI-2 IP instance converts pixel data to AXI4-Streaming outputs, enabling connectivity to other IP cores within Altera's Video and Vision Processing (VVP) Suite.
The FPGA design comprises a MIPI D-PHY and MIPI CSI-2 interface connected to an NVIDIA Holoscan Sensor Bridge IP and Altera's 25GbE MAC IP.
The software comprises a number of demonstration applications running within NVIDIA Holoscan Sensor Bridge SDK.
High-Level Block Diagram of the Holoscan Sensor Bridge System Example Design
Example design build and run instructions can be found here¶
Useful User Manuals and Reference Materials¶
Notices & Disclaimers¶
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Created: June 25, 2026